Clock; Devices; Memory Data Bus Size; Data_Rdy To Write Data Delay - Lattice Semiconductor MachXO2 User Manual

Parameter Settings

Clock

This parameter specifies the frequency of the memory clock to the on-board memory. The frequency is 100 MHz or
less.

Devices

The MachXO2 device family provides a LPDDR JEDEC-compliant PHY and memory controller.
The devices available for evaluation are LCMXO2-2000HC-6BG256CES, LCMXO2-4000HC-6BG256CES and
LCMXO2-7000HC-6BG256CES.

Memory Data Bus Size

The MachXO2 device family provides a 16-bit I/O interface to the LPDDR memory.

Data_rdy to Write Data Delay

User logic is allowed to send the write data to the controller after a one-clock cycle delay with respect to the
datain_rdy signal. Refer to "WRITE" on page 8 for more information.

Clock Width

The controller provides one differential clock for the LPDDR memory.

Setting Tab

Figure 3-3 shows the contents of the Setting tab.
Figure 3-3. Setting Options in the IPexpress Tool

Row Size

This option indicates the Row Address size used in the selected memory configuration. It corresponds to the 1 Gb
LPDDR memory used for this evaluation package.

Column Size

This option indicates the Column Address size used in the selected memory configuration. It corresponds to the 1
Gb LPDDR Memory used for this evaluation package.
IPUG92_01.2, October 2012 16 LPDDR SDRAM Controller User's Guide