Subscribe to Our Youtube Channel
Related Manuals for Lattice Semiconductor CrossLink
Summary of Contents for Lattice Semiconductor CrossLink
- Page 1 CrossLink Programming and Configuration Usage Guide Technical Note FPGA-TN-02014 Version 1.2 December 2017...
-
Page 2: Table Of Contents
Revision History .................................. 28 © 2015-2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. - Page 3 Table 6.2. Configuration Mode/Port Options ........................26 © 2015-2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
-
Page 4: Acronyms In This Document
Slave Serial Peripheral Interface © 2015-2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. -
Page 5: Overview
Optional security bits for design protection © 2015-2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. -
Page 6: Definition Of Terms
This document uses the following terms to describe common functions: BIT – The BIT file is the configuration data for CrossLink that is stored in an external SPI Flash. It is a binary file and is programmed unmodified into the SPI Flash. -
Page 7: Configuration Process And Flow
NVCM space, and as a result is not a factor in the sysCONFIG port priority scheme. © 2015-2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. -
Page 8: Power-Up Sequence
© 2015-2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. -
Page 9: Configuration
© 2015-2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. -
Page 10: Clearing The Configuration Memory And Re-Initialization
4.3. © 2015-2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. -
Page 11: Self-Download Port Pins
Figure 4.2. Period CRESETB is Always Observed © 2015-2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. -
Page 12: Figure 4.3. Configuration From Cresetb Timing
Note that CRESETB is no longer level sensitive. © 2015-2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. -
Page 13: Master And Slave Spi Configuration Port Pins
48 MHz © 2015-2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. - Page 14 CrossLink is recommended. © 2015-2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
-
Page 15: I 2 C Configuration Port Pins
I2C0 USER_SDA pin. © 2015-2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. -
Page 16: Configuration Modes
CrossLink reads the remaining configuration data bytes using the new MCK frequency. © 2015-2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. -
Page 17: Dual Boot Configuration Mode
Refer to the Diamond Online Help for more information about using Diamond implementations. © 2015-2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. -
Page 18: Slave Spi Mode
In the Slave SPI mode, the MLK/SPI_SCK pin becomes SPI_SCK (that is Configuration clock). Input data is read into the CrossLink device on the MOSI pin at the rising edge of SPI_SCK. Output data is valid on the MISO pin at the falling edge of SPI_SCK. -
Page 19: I 2 C Configuration Mode
CRESETB pin is held LOW. © 2015-2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. -
Page 20: Figure 5.2. I 2 C Configuration Logic
C memory transactions to the Configuration Logic operates correctly. © 2015-2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. -
Page 21: Transfr Operation
© 2015-2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. -
Page 22: Figure 5.4. Example Process Flow
I/O pin does not trigger a system crash. © 2015-2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. -
Page 23: Software Selectable Options
Figure 6.1. sysCONFIG Preferences in Global Preferences Tab, Diamond Spreadsheet View © 2015-2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. -
Page 24: Configuration Mode And Port Options
MCCLK_FREQ value. © 2015-2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. -
Page 25: Bitstream Generation Options
GPIO becomes available to the user. © 2015-2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. -
Page 26: Security Options
Hex — CUSTOM_IDCODE is set using eight hexadecimal digits (that is 0-9A-F) © 2015-2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. -
Page 27: Device Wake-Up Sequence
When high, the CDONE pin indicates that configuration is complete and that no errors are detected. © 2015-2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. -
Page 28: References
© 2015-2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. - Page 29 First preliminary release. © 2015-2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
- Page 30 Floor, 111 SW 5 Avenue Portland, OR 97204, USA T 503.268.8000 www.latticesemi.com...
Need help?
Do you have a question about the CrossLink and is the answer not in the manual?
Questions and answers