Frequency Tracking And Phase Locking - GE L30 Instruction Manual

9.1 OVERVIEW
Each relay has a digital clock that determines when to take data samples and which is phase synchronized to all other
clocks in the system and frequency synchronized to the power system frequency. Phase synchronization drives the relative
timing error between clocks to zero, and is needed to control the uncertainty in the phase angle of phasor measurements,
which will be held to under 26 microseconds (0.6 degrees). Frequency synchronization to the power system eliminates a
source of error in phasor measurements that arises when data samples do not exactly span one cycle.
The block diagram for clock control for a two terminal system is shown in Figure 8–4. Each relay makes a local estimate of
the difference between the power system frequency and the clock frequency based on the rotation of phasors. Each relay
also makes a local estimate of the time difference between its clock and the other clocks either by exchanging timing infor-
mation over communications channels or from information that is in the current phasors, depending on whichever one is
more accurate at any given time. A loop filter then uses the frequency and phase angle deviation information to make fine
adjustments to the clock frequency. Frequency tracking starts if the current at one or more terminals is above 0.125 pu of
nominal; otherwise, the nominal frequency is used.
Figure 9–1: BLOCK DIAGRAM FOR CLOCK SYNCHRONIZATION IN A TWO-TERMINAL SYSTEM
The L30 provides sensitive digital current differential protection by computing differential current from current phasors. To
improve sensitivity, the clocks are controlling current sampling are closely synchronized via the ping-pong algorithm. How-
ever, this algorithm assumes the communication channel delay is identical in each direction. If the delays are not the same,
the error between current phasors is equal to half of the transmit-receive time difference. If the error is high enough, the
relay perceives the "apparent" differential current and misoperates.
For applications where the communication channel is not symmetric (for example, SONET ring), the L30 allows the use of
GPS (Global Positioning System) to compensate for the channel delay asymmetry. This feature requires a GPS receiver to
provide a GPS clock signal to the L30 IRIG-B input. With this option there are two clocks as each terminal: a local sampling
9
clock and a local GPS clock. The sampling clock controls data sampling while the GPS clock provides an accurate, abso-
lute time reference used to measure channel asymmetry. The local sampling clocks are synchronized to each other in
phase and to the power system in frequency. The local GPS clocks are synchronized to GPS time using the externally pro-
vided GPS time signal.
GPS time stamp is included in the transmitted packet along with the sampling clock time stamp. Both sampling clock devia-
tion and channel asymmetry are computed from the four time-stamps. One half of the channel asymmetry is then sub-
tracted from the computed sampling clock deviation. The compensated deviation drives the phase and frequency lock loop
9-6
RELAY 1
f
+
_
Compute
Frequency
f – f1 f1
Deviation
+
Phase Frequency
+
Loop Filter
+
ϕ1
Ping-Pong
ϕ ϕ
( 2 – 1)/2
Phase
Deviation
θ θ
GPS
( 2 – 1)/2
Phase
Deviation
θ
GPS
Clock
L30 Line Current Differential System

9.1.9 FREQUENCY TRACKING AND PHASE LOCKING

RELAY 2
System f
Frequency
+
_
Compute
Frequency
f2
Deviation
Phase Frequency
Loop Filter
ϕ2
Ping-Pong
time stamps
Phase
Deviation
GPS
time stamps
Phase
Deviation
θ
GPS
Clock
9 THEORY OF OPERATION
f – f2
+
+
+
ϕ ϕ
( 2 – 1)/2
θ θ
( 2 – 1)/2
831026A1.CDR
GE Multilin