HPE FlexFabric 5700 Series Network Management And Monitoring Configuration Manual page 59

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3.
The member clock sends a Delay_Req message to calculate the transmission delay in the
reverse direction, and records the sending time t3. Upon receiving the message, the master
clock records the receiving time t4.
4.
The master clock returns a Delay_Resp message carrying time t4.
From the above process, the member clock collects four timestamps, t1 to t4, and obtains the
round-trip delay to the master clock by using the following calculation:
[(t2 – t1) + (t4 – t3)]
The member clock also obtains the one-way delay by using the following calculation:
[(t2 – t1) + (t4 – t3)] / 2
The offset between the member and master clocks is obtained by using the following calculation:
(t2 – t1) – [(t2 – t1) + (t4 – t3)] / 2
[(t2 – t1) – (t4 – t3)] / 2
Depending on whether to send Follow_Up messages, the Request_Response mechanism includes
two modes: single-step and two-step.
In single-step mode, t1 is carried in the Sync message, and no Follow_Up message is sent.
In two-step mode, t1 is carried in the Follow_Up message.
Peer Delay
Figure 20 Operation procedure of the Peer Delay mechanism
Master clock
t1
t4
t5
The Peer Delay mechanism uses Pdelay messages to calculate link delay, which applies only to
point-to-point delay measurement.
using the two-step mode.
1.
The master clock sends a Sync message to the member clock, and records the sending time t1.
Upon receiving the message, the member clock records the receiving time t2.
2.
After sending the Sync message, the master clock sends a Follow_Up message carrying time
t1 immediately.
3.
The member clock sends a Pdelay_Req message to calculate the transmission delay in the
reverse direction, and records the sending time t3. Upon receiving the message, the master
clock records the receiving time t4.
4.
The master clock returns a Pdelay_Resp message carrying time t4, and records the sending
time t5. Upon receiving the message, the member clock records the receiving time t6.
Member clock
Timestamps
known by
member clock
t2
t2
t1, t2
t3
t1, t2, t3
t6
t1, t2, t3, t4, t6
t1, t2, t3, t4, t5, t6
Figure 20
shows an example of the Peer Delay mechanism by
50

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