Segger J-Link User Manual page 42

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1.6.2.1 Limitations of PC-side implementations
• Instability, especially on slow targets
Due to the fact that a lot of USB transactions would cause a very bad perfor-
mance of J-Link, on PC-side implementations the assumption is made that the
CPU/Debug interface is fast enough to handle the commands/requests without
the need of waiting. So, when using the PC-side-intelligence, stability can not be
guaranteed in all cases, especially if the target interface speed (JTAG/SWD/...) is
significantly higher than the CPU speed.
• Poor performance
Since a lot more data has to be transferred over the host interface (typ. USB),
the resulting download speed is typically much lower than for implementations
with intelligence in the firmware, even if the number of transactions over the
host interface is limited to a minimum (fast mode).
• No support
Please understand that we can not give any support if you are running into prob-
lems when using a PC-side implementation.
Note: Due to these limitations, we recommend to use PC-side implementations
for evaluation only.
J-Link / J-Trace (UM08001)
CHAPTER 1
© 2004-2011 SEGGER Microcontroller GmbH & Co. KG
Introduction