Segger J-Link User Manual page 223

Jtag emulators for arm cores
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A
Adaptive clocking ............................... 216
Application Program Interface .............. 216
B
Big-endian ........................................ 216
C
Cache cleaning .................................. 216
Coprocessor ...................................... 216
D
Dirty data ......................................... 216
Dynamic Linked Library (DLL) .............. 216
E
Embedded Trace Buffer (ETB) .......197, 216
Embedded Trace Macrocell (ETM) ..193, 216
EmbeddedICE ................................... 216
H
Halfword ........................................... 216
Host ................................................. 216
I
ICache ............................................. 216
ICE Extension Unit ............................. 216
ID ................................................... 217
IEEE 1149.1 ...................................... 217
Image .............................................. 217
In-Circuit Emulator ............................ 217
Instruction Register ............................ 217
IR .................................................... 217
J
J-Flash ARM ........................................86
J-Link
Adapters ........................................ 187
Developer Pack DLL ...........................92
Supported chips ....................... 144–145
J-Link / J-Trace (UM08001)
Index
J-Link ARM Flash DLL ........................... 92
J-Link Commander .............................. 80
J-Link GDB Server ............................... 88
J-Link RDI .......................................... 87
J-Link STR9 Commander ...................... 81
J-Link TCP/IP Server ............................ 84
J-Mem Memory Viewer ......................... 85
Joint Test Action Group (JTAG) .............217
JTAG ................................................190
TAP controller ..................................191
JTAGLoad ........................................... 92
L
Little-endian ......................................217
M
Memory coherency .............................217
Memory management unit (MMU) ........217
Memory Protection Unit (MPU) .............217
Multi-ICE ..........................................217
N
nTRST ...................................... 174, 217
O
Open collector ...................................217
P
Processor Core ..................................218
Program Status Register (PSR) ............218
R
RDI Support ....................................... 87
Remapping ........................................218
Remote Debug Interface (RDI) .............218
RESET ..............................................217
RTCK ................................................218
RTOS ................................................218
© 2004-2011 SEGGER Microcontroller GmbH & Co. KG
223

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