Atmel; At91Sam7 - Segger J-Link User Manual

158
7.2

ATMEL

J-Link has been tested with the following ATMEL devices, but should work with any
ARM7/9 and Cortex-M3 device:
• AT91SAM7A3
• AT91SAM7S32
• AT91SAM7S321
• AT91SAM7S64
• AT91SAM7S128
• AT91SAM7S256
• AT91SAM7S512
• AT91SAM7SE32
• AT91SAM7SE256
• AT91SAM7SE512
• AT91SAM7X128
• AT91SAM7X256
• AT91SAM7X512
• AT91SAM7XC128
• AT91SAM7XC256
• AT91SAM7XC512
• AT91RM9200
• AT91SAM9260
• AT91SAM9261
• AT91SAM9262
• AT91SAM9263
If you experience problems with a particular device, do not hesitate to contact Seg-
ger.
7.2.1

AT91SAM7

All devices of this family are supported by J-Link.
7.2.1.1 Reset strategy
The reset pin of the device is per default disabled. This means that the reset strate-
gies which rely on the reset pin (low pulse on reset) do not work per default. For this
reason a special reset strategy has been made available.
It is recommended to use this reset strategy. This special reset strategy resets the
peripherals by writing to the RSTC_CR register. Resetting the peripherals puts all
peripherals in the defined reset state. This includes memory mapping register, which
means that after reset flash is mapped to address 0. It is also possible to achieve the
same effect by writing 0x4 to the RSTC_CR register located at address 0xfffffd00.
This information is applicable to the following devices:
• AT91SAM7S (all devices)
• AT91SAM7SE (all devices)
• AT91SAM7X (all devices)
• AT91SAM7XC (all devices)
• AT91SAM7A (all devices)
7.2.1.2 Memory mapping
Either flash or RAM can be mapped to address 0. After reset flash is mapped to
address 0. In order to map RAM to address 0, a 1 can be written to the RSTC_CR reg-
ister. Unfortunately, this remap register is a toggle register, which switches between
RAM and flash with every time bit zero is written.
In order to achieve a defined mapping, there are two options:
1. Use the software reset described above.
2. Test if RAM is located at 0 using multiple read/write operations and testing the
J-Link / J-Trace (UM08001)
CHAPTER 7
© 2004-2011 SEGGER Microcontroller GmbH & Co. KG
Device specifics