Pinout - Segger J-Link User Manual

180
8.2.2

Pinout

The following table lists the JTAG+Trace connector pinout. It is compatible to the
"Trace Port Physical Interface" described in [ETM], 8.2.2 "Single target connector
pinout".
PIN SIGNAL
1 NC
2 NC
3 NC
4 NC
5 GND
6 TRACECLK
7 DBGRQ
8 DBGACK
9 RESET
10 EXTTRIG
11 TDO
12 VTRef
13 RTCK
14 VSupply
15 TCK
16 Trace signal 12
17 TMS
18 Trace signal 11
19 TDI
20 Trace signal 10
21 nTRST
Table 8.5: JTAG+Trace connector pinout
J-Link / J-Trace (UM08001)
CHAPTER 8
No connected.
No connected.
No connected.
No connected.
Signal ground.
Clocks trace data on rising edge or both edges.
Debug request.
Debug acknowledge from the test chip, high when in
debug state.
Open-collector output from the run control to the target
system reset.
Optional external trigger signal to the Embedded trace
Macrocell (ETM). Not used. Leave open on target system.
Test data output from target JTAG port.
Signal level reference. It is normally fed from Vdd of the
target board and must not have a series resistor.
Return test clock from the target JTAG port.
Supply voltage. It is normally fed from Vdd of the target
board and must not have a series resistor.
Test clock to the run control unit from the JTAG port.
Trace signal. For more information, please refer to
Assignment of trace information pins between ETM archi-
tecture versions on page 182.
Test mode select from run control to the JTAG port.
Trace signal. For more information, please refer to
Assignment of trace information pins between ETM archi-
tecture versions on page 182.
Test data input from run control to the JTAG port.
Trace signal. For more information, please refer to
Assignment of trace information pins between ETM archi-
tecture versions on page 182.
Active-low JTAG reset
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Target interfaces and adapters
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