Segger J-Link User Manual page 25

LOW level input voltage (V
HIGH level input voltage (V
LOW level output voltage (V
load of 10 kOhm
HIGH level output voltage (V
load of 10 kOhm
LOW level output voltage (V
load of 10 kOhm
HIGH level output voltage (V
load of 10 kOhm
SWO sampling frequency
Data input rise time (T
Data input fall time (T
Data output rise time (T
Data output fall time (T
Clock rise time (T
Clock fall time (T
Table 1.1: J-Link ARM specifications
1.3.2.3 Download speed
The following table lists performance values (Kbytes/s) for writing to memory (RAM):
Hardware
J-Link Rev. 6 — 8
Table 1.2: Download speed differences between hardware revisions
All tests have been performed in the testing environment which is described on Mea-
suring download speed on page 208.
The actual speed depends on various factors, such as JTAG/SWD, clock speed, host
CPU core etc.
1.3.2.4 Hardware versions
Versions 1-4
Obsolete.
Version 5.0
Identical to version 4.0 with the following exception:
• Uses a 32-bit RISC CPU.
• Maximum download speed (using DCC) is over 700 Kbytes/second.
• JTAG speed: Maximum JTAG frequency is 12 MHz; possible JTAG speeds are:
48 MHz / n, where n is 4, 5, ..., resulting in speeds of:
12.000 MHz (n = 4)
9.600 MHz (n = 5)
8.000 MHz (n = 6)
6.857 MHz (n = 7)
6.000 MHz (n = 8)
J-Link / J-Trace (UM08001)
)
IL
)
IH
For 1.8V <= V
) with a
OL
) with a
OH
For 3.6 <= V
) with a
OL
) with a
OH
JTAG/SWD Interface, Timing
)
rdi
)
fdi
)
rdo
)
fdo
)
rc
)
fc
ARM7
via JTAG
720 Kbytes/s
(12MHz JTAG)
V <= 40% of V
IL IF
V >= 60% of V
IH IF
<= 3.6V
IF
V <= 10% of V
OL IF
V >= 90% of V
OH IF
<= 5V
IF
V <= 20% of V
OL IF
V >= 80% of V
OH IF
Max. 6 MHz
T <= 20ns
rdi
T <= 20ns
fdi
T <= 10ns
rdo
T <= 10ns
fdo
T <= 10ns
rc
T <= 10ns
fc
ARM9
via JTAG
550 Kbytes/s
(12MHz JTAG)
© 2004-2011 SEGGER Microcontroller GmbH & Co. KG
25
Cortex-M3
via SWD
180 Kbytes/s
(12 MHz SWD)