20-Pin Jtag/Swd Connector; Pinout For Jtag - Segger J-Link User Manual

174
8.1

20-pin JTAG/SWD connector

8.1.1

Pinout for JTAG

J-Link and J-Trace have a JTAG connector compati-
ble to ARM's Multi-ICE. The JTAG connector is a 20
way Insulation Displacement Connector (IDC) keyed
box header (2.54mm male) that mates with IDC
sockets mounted on a ribbon cable.
The following table lists the J-Link / J-Trace JTAG
pinout.
PIN SIGNAL
1 VTref
Not con-
2
nected
3 nTRST
5 TDI
7 TMS
9 TCK
11 RTCK
13 TDO
15 RESET
17 DBGRQ
5V-Sup-
19
ply
Table 8.1: J-Link / J-Trace pinout
J-Link / J-Trace (UM08001)
CHAPTER 8
TYPE
This is the target reference voltage. It is used to check if
the target has power, to create the logic-level reference for
Input the input comparators and to control the output logic levels
to the target. It is normally fed from Vdd of the target board
and must not have a series resistor.
NC This pin is not connected in J-Link.
JTAG Reset. Output from J-Link to the Reset signal of the
target JTAG port. Typically connected to nTRST of the target
Output
CPU. This pin is normally pulled HIGH on the target to avoid
unintentional resets when there is no connection.
JTAG data input of target CPU.- It is recommended that this
Output pin is pulled to a defined state on the target board. Typically
connected to TDI of the target CPU.
JTAG mode set input of target CPU. This pin should be
Output pulled up on the target. Typically connected to TMS of the
target CPU.
JTAG clock signal to target CPU. It is recommended that this
Output pin is pulled to a defined state of the target board. Typically
connected to TCK of the target CPU.
Return test clock signal from the target. Some targets must
synchronize the JTAG inputs to internal clocks. To assist in
meeting this requirement, you can use a returned, and
Input retimed, TCK to dynamically control the TCK rate. J-Link
supports adaptive clocking, which waits for TCK changes to
be echoed correctly before making further changes. Con-
nect to RTCK if available, otherwise to GND.
JTAG data output from target CPU. Typically connected to
Input
TDO of the target CPU.
Target CPU reset signal. Typically connected to the RESET
I/O pin of the target CPU, which is typically called "nRST",
"nRESET" or "RESET".
This pin is not connected in J-Link. It is reserved for com-
patibility with other equipment to be used as a debug
NC
request signal to the target system. Typically connected to
DBGRQ if available, otherwise left open.
This pin can be used to supply power to the target hard-
ware. Older J-Links may not be able to supply power on this
Output pin. For more information about how to enable/disable the
power supply, please refer to Target power supply on
page 176.
Target interfaces and adapters
VTref
nTRST
TDI
TMS
TCK
RTCK
TDO
RESET
DBGRQ
5V-Supply
Description
© 2004-2011 SEGGER Microcontroller GmbH & Co. KG
1 2 NC
3 4 GND
5 6
GND
7 8
GND
9 10
GND
11 12
GND
13 14 GND
15 16 GND
17 18 GND
19 20 GND