Segger J-Link User Manual page 35

Jtag emulators for arm cores
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Clock fall time (T
Power supply
Target interface voltage (V
Voltage interface low pulse (V
Voltage interface high pulse (V
TRACECLK low pulse width (T
TRACECLK high pulse width (T
Data rise time (T
Data fall time (T
Clock rise time (T
Clock fall time (T
Data setup time (T
Data hold time (T
Table 1.9: J-Trace for Cortex-M3 specifications
1.3.8.3 Download speed
The following table lists performance values (Kbytes/s) for writing to memory (RAM):
J-Trace for Cortex-M3 V2
J-Trace for Cortex-M V3.1
Table 1.10: Download speed differences between hardware revisions
The actual speed depends on various factors, such as JTAG, clock speed, host CPU
core etc.
1.3.8.4 Hardware versions
Version 2
Obsolete.
Version 3.1
Identical to version 2.0 with the following exceptions:
Hi-Speed USB
Voltage range for trace signals extended to 1.2 - 3.3 V
Higher download speed
J-Link / J-Trace (UM08001)
)
fc
Trace Interface, Electrical
)
IF
)
IL
)
IH
Trace Interface, Timing
)
wl
)
wh
)
rd
)
fd
)
rc
)
fc
)
s
)
h
Hardware
Max. 10ns
USB powered
Max. 50mA + Target Supply current.
1.2V ... 5V
Max. 40% of V
IF
Min. 60% of V
IF
Min. 2ns
Min. 2ns
Max. 3ns
Max. 3ns
Max. 3ns
Max. 3ns
Min. 3ns
Min. 2ns
Cortex-M3
190 Kbytes/s (12MHz SWD)
760 KB/s (12 MHz JTAG)
190 Kbytes/s (12MHz SWD)
1440 KB/s (25 MHz JTAG)
© 2004-2011 SEGGER Microcontroller GmbH & Co. KG
35

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