Mitsubishi Electric Q68AD-G User Manual page 75

Channel isolated analog-digital converter module/ channel isolated analog-digital converter module (with signal conditioning function)
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3
SPECIFICATIONS
(2) Buffer memory assignment of Q66AD-DG
Address
Hexadecimal Decimal
0
0
H
1
1
H
2
2
H
3
3
H
4
4
H
5
5
H
6
6
H
7
7
H
to
to
9
9
H
A
10
H
B
11
H
C
12
H
D
13
H
E
14
H
F
15
H
10
16
H
11
17
H
12
18
H
13
19
H
14
20
H
15
21
H
16
22
H
17
23
H
18
24
H
19
25
H
Do not write data from system area or sequence program to the buffer memory
area where writing is disabled.
Doing so may cause malfunction.
Table3.9 Buffer memory assignment of Q66AD-DG (1/5)
Description
A/D conversion enable/disable setting
CH1 Average time/Average number of times/
Moving average/Time constant settings
CH2 Average time/Average number of times/
Moving average/Time constant settings
CH3 Average time/Average number of times/
Moving average/Time constant settings
CH4 Average time/Average number of times/
Moving average/Time constant settings
CH5 Average time/Average number of times/
Moving average/Time constant settings
CH6 Average time/Average number of times/
Moving average/Time constant settings
System area
A/D conversion completed flag
CH1 Digital output value
CH2 Digital output value
CH3 Digital output value
CH4 Digital output value
CH5 Digital output value
CH6 Digital output value
System area
Error code
Setting range(CH1 to CH4)
Setting range(CH5,CH6)
Offset/gain setting mode offset specification
Offset/gain setting mode gain specification
Averaging process specification (CH1 to CH4)
Averaging process specification (CH5 to CH6)
*1 Indicates whether reading from and writing to a sequence program are enabled.
R : Read enabled
W : Write enabled
*2 When writing data to the buffer memory, always use the interlock condition (buffer memory write
condition) of the following I/O signals.
Buffer memory writing condition
Y9
X9
Writing
Operating
Operating
condition
condition
request
setting
setting
request
completed
flag
Default
R/W
003F
R/W
H
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R/W
0
R/W
0
R/W
0
R/W
MOV
3.4 Buffer Memory
3.4.1 Buffer memory assignment
1
2
*1
Reference
3
*2
Section 3.4.2
*2
*2
*2
Section 3.4.3
4
*2
*2
*2
5
Section 3.4.4
Section 3.4.5
6
Section 3.4.6
Section 3.4.7
Section 3.4.8
7
*2
Section 3.4.9
*2
8
3
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