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S1R72104 Technical Manual
7.3.20 DMA Transfer Byte Count 0 (DTBC0) R/W
Sets the least significant byte of the byte-length (3 bytes) for DMA transfer.
7
6
5
DBC7
DBC6
DBC5
7.3.21 CONFIG0 (CONFIG0) R/W
Sets the operation mode of the IC.
7
6
5
ACP
INTLV
PSLV
BIT7 ACTIVATE PORT
After reset, the port interface is in All Pins Input mode. Setting this bit to HIGH activates the port.
BIT6 INTERRUPT LEVEL
Decides the level of the signal interrupting CPU.
0: Active LOW (Output to XINT is 0/Hi-Z)
1: Active HIGH (Output to XINT is 1/0)
BIT5 PORT SLAVE
Decides the operation mode of the port.
0: Master mode (PDREQ = input; XPDACK/XPRD/XPWR = output)
1: Slave mode (PDREQ = output; XPDACK/XPRD/XPWR = input)
BIT3 PDREQ LEVEL
Decides the operation mode of PDREQ signal.
0: Positive logic
1: Negative logic
BIT2 SWAP PORT INTERFACE BUS
Swaps the higher 8 bits with lower ones when the port interface is used with 16-bit width.
0: Lower 8 bits data is transferred first.
1: Higher 8 bits data is transferred first.
BIT1 ODD BYTE START
Setting this bit to HIGH causes the 8 bits data, which should be sent later because of the SWAP setting when the port
interface is used with 16-bit width, to be transferred first.
It is effective only for the first one byte.
BIT0 PORT INTERFACE 8 BIT BUS
Set this bit to HIGH to use the port interface with 8-bit width.
Only the lower 8 bits are valid. Connect the higher 8 bits to GND or HV
18
4
3
2
DBC4
DBC3
DBC2
4
3
2
-
PRQLV
SWAP
1
0
1Bh
DBC1
DBC0
1
0
1Ch
ODS
BUS8
PORT INTERFACE 8 BIT BUS
ODD BYTE START
SWAP PORT INTERFACE BUS
PDREQ LEVEL
PORT SLAVE
INTERRUPT LEVEL
ACTIVATE PORT
DD
EPSON
externally.
Rev.1.1
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