Epson S1R72104 Technical Manual page 29

S1R72104 Technical Manual
It causes interruption.
CPU reads a command from FIFO
In Initiator mode
CPU issues this command after setting the command byte number in NON-DMA data-size register.
Then it writes the command data in FIFO.
The IC acts as follows:
Negates XSACK if it is asserted at the start of execution.
Transfers the command data in FIFO after checking the command phase at the timing of assertion of XSREQ.
Suspends REQ-ACK hand-shake until FIFO becomes full of data, if FIFO was empty.
After that, it sets GOOD bit of MAININT register.
It causes interruption.
If any other phase is found when the command phase is checked:
Sets ILPHS of SCSIINT1, causing interruption.
Caution: Be sure that data is written in FIFO after the number of bytes to be transferred was set.
DMA_Data_Out(13H)
Executes SCSI data-out phase.
Transfers data between port and SCSI usually.
Setting FIFO bit (DMACTL register: bit 1) causes the transfer between CPU and SCSI.
Valid only in the connected condition. It can be issued in either Target or Initiator mode.
If issued in the disconnected condition, it sets SCSIINT2 and CMDER bits, causing interruption.
In Target mode
Combination of this command issued and the AND condition of DTGO bit of DMACTL register starts DMA
transfer.
When transfer of the count value set in DTBC register is over, the command ends, GOOD and DTCMP bits of
MAININT register are set, and interruption is caused.
In Initiator mode
Negates XSACK if it is asserted at the start of execution.
After the data-out phase was checked at the timing of assertion of XSREQ, the AND condition of DTGO bit of
DMACTL register starts actual DMA transfer. When the transfer of the count value set in DTBC register is over,
the command ends, GOOD and DTCMP bits of MAININT register are set, and interruption is caused.
If any other phase is found when the data-out phase is checked, ILPHS of SCSIINT1 is set, and interruption is
caused.
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