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8.4.3 Port Interface
8.4.3.1 DMA Read (PSLV=1: Slave mode)
PDREQ(0)
(PRQLV=1)
XPDACK(I)
XPRD(I)
PD15-0(0)
XPWR(I)
Symbol
XPWR → XPDACK ↓
T
301
XPDACK setup time
XPDACK ↑ → XPWR
T
302
XPDACK hold time
XPRD ↓ → PDREQ negate
T
303
PDREQ negate delay time
XPDACK ↓ → XPRD ↓
T
304
XPRD setup time
XPRD ↓ → XPRD ↑
T
305
XPRD assert pulse width
XPRD ↑ → XPRD ↓
T
306
XPRD negate pulse width
XPRD ↑ → XPDACK ↑
T
307
XPRD hold time
XPRD ↓ → PD
T
308
Data output delay time Note 1
XPRD ↑ → PD(Hi-Z)
T
309
Data bus negate time Note 1
Note 1: Data is output to PD only while both XPDACK and XPRD are asserted.
PD is always in Input mode except such time.
Note 2: The value in ( ) is guaranteed by limiting load capacitance, 15pF, and 1TTL to driving.
Rev.1.1
Direction of data transfer
T
T
304
305
T
308
T
301
Specification
S1R72104 Technical Manual
Prosessor
S1R72104
T
306
T
309
Min.
Typ.
5
-
5
-
10
-
0
-
30
-
30
-
0
-
0
-
6
-
EPSON
HOST
T
303
T
307
T
302
Max.
Unit
-
ns
-
ns
40
ns
(35) Note 1
-
ns
-
ns
-
ns
-
ns
25
ns
(20) Note 2
40
ns
49
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