Epson S1R72104 Technical Manual page 30

Non-DMA_Data_Out(14H)
Executes the data-out phase between SCSI and CPU interface.
Valid only in the connected condition. It can be issued in either Target or Initiator mode.
If issued in the disconnected condition, it sets SCSIINT2 and CMDER bits, causing interruption.
In Target mode
Setting data bytes to be transferred in NON-DMA data-size register issues this command.
CPU reads data from inside of FIFO by referring to FIFO status.
The IC acts as follows:
Enters data bytes set into FIFO after setting the data-out phase.
REQ-ACK hand-shake is suspended until FIFO has some space, if FIFO was full.
After that, it sets GOOD bit of MAININT register.
It causes interruption.
In Initiator mode
Setting number of bytes to be transferred in NON-DMA data-size register issues this command.
CPU writes data into FIFO referring to FIFO status.
The IC acts as follows:
Negates XSACK if it is asserted at the start of execution.
Transfers data bytes set from FIFO after checking the data-out phase at the timing when XSREQ is asserted.
Suspends REQ-ACK hand-shake until FIFO becomes full of data, if FIFO was empty
After that, it sets GOOD bit of MAININT register.
It causes interruption.
Caution: Be sure that data is written in FIFO after the number of bytes to be transferred was set.
* Non-DMA_Data_Out can be implemented by setting FIFObit to DMA_Data_Out mentioned above.
Non-DMA_Data_Out can be used only for asynchronous transfer. Se we recommend that the operations
mentioned above be implemented with the combination of DMA_Data_Out and FIFObit.
DMA_Data_In(15H)
Executes SCSI data-in phase.
Transfers data between port and SCSI usually.
Setting FIFO bit (DMACTL register: bit 1) causes the transfer between CPU and SCSI.
Valid only in the connected condition. It can be issued in either Target or Initiator mode.
If issued in the disconnected condition, it sets SCSIINT2 and CMDER bits, causing interruption.
In Target mode
Combination of this command issued and the AND condition of DTGO bit of DMACTL register starts DMA
transfer.
When transfer of the count value set in DTBC register is over, the command ends, GOOD and DTCMP bits of
MAININT register are set, and interruption is caused.
In Initiator mode
Negates XSACK if it is asserted at the start of execution.
After the data-out phase was checked at the timing of assertion of XSREQ, the AND condition of DTGO bit of
DMACTL register starts actual DMA transfer. When the transfer of the count value set in DTBC register is over,
the command ends, GOOD and DTCMP bits of MAININT register are set, and interruption is caused.
If any other phase is found when the data-in phase is checked:
Sets ILPHS of SCSIINT1, causing interruption.
Rev.1.1
S1R72104 Technical Manual
EPSON 25