Figure 31. I 2 S Slave Timing Diagram (Philips Protocol) - STMicroelectronics STM32F042F4 Manual

STM32F042x4 STM32F042x6
Symbol
t
su(SD_MR)
Data input setup time
t
su(SD_SR)
(2)
t
h(SD_MR)
Data input hold time
(2)
t
h(SD_SR)
(2)
t
v(SD_MT)
Data output valid time
(2)
t
v(SD_ST)
t
h(SD_MT)
Data output hold time
t
h(SD_ST)
1. Data based on design simulation and/or characterization results, not tested in production.
2. Depends on f . For example, if f
PCLK
1. Measurement points are done at CMOS levels: 0.3 × V
2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.
2
Table 64. I S characteristics
Parameter
Master receiver
Slave receiver
Master receiver
Slave receiver
Master transmitter
Slave transmitter
Master transmitter
Slave transmitter
= 8 MHz, then T
PCLK
2
Figure 31. I S slave timing diagram (Philips protocol)
DocID025832 Rev 5
(1)
(continued)
Conditions
= 1/f = 125 ns.
PCLK PLCLK
and 0.7 × V
DDIOx
Electrical characteristics
Min Max
6 -
2 -
4 -
0.5 -
- 4
- 20
0 -
13 -
.
DDIOx
Unit
ns
87/117
89