Table 62. I 2 C Analog Filter Characteristics; Table 63. Spi Characteristics - STMicroelectronics STM32F042F4 Manual

Electrical characteristics
Symbol
t
AF
1. Guaranteed by design, not tested in production.
2. Spikes with widths below t
3. Spikes with widths above t
2
SPI/I S characteristics
Unless otherwise specified, the parameters given in
are derived from tests performed under the ambient temperature, f
supply voltage conditions summarized in
Refer to
Section 6.3.14: I/O port characteristics
function characteristics (NSS, SCK, MOSI, MISO for SPI and WS, CK, SD for I
Symbol Parameter
f
SCK
SPI clock frequency
1/t
c(SCK)
t SPI clock rise and fall
r(SCK)
t time
f(SCK)
t NSS setup time
su(NSS)
t NSS hold time
h(NSS)
t
w(SCKH)
SCK high and low time
t
w(SCKL)
t
su(MI)
Data input setup time
t
su(SI)
t
h(MI)
Data input hold time
t
h(SI)
(2)
t Data output access time
a(SO)
(3)
t Data output disable time
dis(SO)
t Data output valid time
v(SO)
t Data output valid time
v(MO)
t
h(SO)
Data output hold time
t
h(MO)
SPI slave input clock
DuCy(SCK)
duty cycle
1. Data based on characterization results, not tested in production.
2. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data.
3. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z
84/117
2
Table 62. I C analog filter characteristics
Parameter
Maximum width of spikes that are
suppressed by the analog filter
are filtered.
AF(min)
are not filtered
AF(max)

Table 63. SPI characteristics

Conditions
Master mode
Slave mode
Capacitive load: C = 15 pF
Slave mode
Slave mode
Master mode, f
presc = 4
Master mode
Slave mode
Master mode
Slave mode
Slave mode, f
Slave mode
Slave mode (after enable edge)
Master mode (after enable edge)
Slave mode (after enable edge)
Master mode (after enable edge)
Slave mode
DocID025832 Rev 5
Min
(2)
50
Table 63
Table 21: General operating
for more details on the input/output alternate
(1)
2Tpclk + 10
= 36 MHz,
PCLK
Tpclk/2 -2
= 20 MHz
PCLK
STM32F042x4 STM32F042x6
(1)
Max
(3)
260
for SPI or in
Table 64
frequency and
PCLKx
conditions.
2
S).
Min Max
- 18
- 18
- 6
4Tpclk -
-
Tpclk/2 + 1
4 -
5 -
4 -
5 -
0 3Tpclk
0 18
- 22.5
- 6
11.5 -
2 -
25 75
Unit
ns
2
for I S
Unit
MHz
ns
ns
%