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Cybernet Elite-4i User Guide
4.4.3 Advanced Chipset Features
If the ADVANCED CHIPSET FEATURES option is selected from the main menu,
the screen below will appear.
DRAM Timing Selectable
x CAS Latency Time
x Active to Precharge Delay
x DRAM RAS# to CAS# Delay
x DRAM RAS# Precharge
Memory Frequency For
System BIOS Cacheable
Video BIOS Cacheable
Memory Hole at 15M-16M
AGP Aperture Size (MB)
Init Display First
** On-Chip VGA Setting **
On-Chip VGA
On-Chip Frame Buffer Size
Boot Display
áâßà Move Enter:Select +/-/PU/PD:Value F10:Save
F5: Previous Values
Figure 37 Advanced Chipset Features Screen
CAS Latency Time
When synchronous DRAM is installed, the number of clock cycles of CAS latency
depends on the DRAM timing. The default setting is 2.5T.
Setting Options: 2T, 2.5T, 3T.
System BIOS Cacheable
Selecting Enabled allows caching of the system BIOS ROM at an address resulting
in better system performance. However, if any program writes to this memory
area, a system error may result. The default setting is Enabled.
Setting Options: Enabled, Disabled.
Video BIOS Cacheable
Selecting ' Enabled' allows caching of the video RAM, resulting in better system
performance. However, if any program writes to this memory area, a system error
may result. The default setting is Disabled.
Setting Options: Enabled, Disabled.
42
Phoenix – AwardBIOS CMOS Setup Utility
Advanced Chipset Features
[By SPD]
2.5
7
3
3
[Auto]
[Enabled]
[Disabled]
[Disabled]
[128]
[Onboard/AGP]
[Enabled]
[16MB]
[Auto]
F6: Fail-safe defaults
Item Help
Menu Level >
ESC:Exit F1:General Help
F7:Optimized Defaults
C M O S S e t u p U t i l i t y
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