Samsung OFFICESERV 7100 Service Manual page 83

Six-port, 10/100 Mbps integrated switch controller-fully non-blocking configuration
Five integrated 10/100 Base-T/TX IEEE 802.3u compliant transceivers
Integrated full-duplex capable 802.3x compliant MACs
64 KB on-chip packet buffer
Media Independent Interface(MII) provided for an additional TX/FX uplink to PHY or
MAC
Integrated address Management-supports(~ 1 K unicast addresses)
Port mirroring and Layer-3 IGMP snooping
802.1p QoS packet classification(4 priority queue and DiffServ DSCP Priority)
16 entries 802.1q-based and Port-based VLAN
Supports 802.1x EAPOL higher layer protocol
EEPROM(93C46, un-managed capabilities)
25-MHz crystal or oscillator
Low-Power 3.3/1.8 V, 0.18 um CMOS technology
HP auto_MDIX function hardware selectable
128-pin MQFP package
Ingress/egress rate control
Protected port capability
DTE/DPM power over Ethernet detection
CPU Interface
For BCM5325E of 4SWM, the management function is controlled by Mindspeed Processor
in MP10/11. The communication between BCM5325 and the processor is established
through the Synchronous Serial Peripheral Interconnect(SPI) bus. SPI bus is composed of
four pins, Serial Clock(SCK), Slave Select(SS), Master-in/Slave-out(MISO), and Master-
out/Slave-in(MOSI), and BCM5325E always operates in slave mode.
SPI bus is shared with the EEPROM interface, and decided depending on the BCM5325E
pin #47(CPU_EEPROM_SEL) status. If High, it is SPI mode. Thus, in 4SWM, pull-up is
performed.
BCM5325E management indicates the register setting and reading of BCM5325.
BCM5325E register is divided into pages of each function.
That is, it has the tree structure like page
© SAMSUNG Electronics Co., Ltd.
OfficeServ 7100 Service Manual
address.
2-49