Samsung OFFICESERV 7100 Service Manual page 56

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SCC
SMC1: Debugging port to be used for engineers
Clock
The CPU clock uses 50 MHz as the main clock oscillator.
The synchronization of the system clock is performed by the PLL circuit of a MP40
board.
4.096 MHz, 8.192 MHz, FOI and FSX are supplied by the mother board.
4.096 MHz of the mother board is supplied to SCLKX/SCLKR of PEF2256H.
The active signal displaying the Valid Reference clock is received in the CPU port.
Boot ROM(Flash ROM)
512 Kbytes flash ROM(SST39VF040) is used for the Boot ROM.
The Boot ROM uses a socket and stores the boot program and DB information.
Application ROM (Flash ROM)
Application ROM uses 4 Mbytes flash ROM(AM29LV320D).
Application ROM is used as and stores application programs.
SDRAM
SDRAM uses 16 Mbytes DRAM(K4S641632) and consists of two 8 Mbytes elements.
The main program resides in the SDRAM and the SDRAM stores the data for the system
processing. The RAM backup is not required.
The access time to SDRAM is set as short as possible for the maximum system
performance.
WATCH DOG
WATCH DOG is the function that recovers the system when a board is malfunction.
It restarts when it operates abnormally for five seconds.
LAN Interface
LAN access is available with no additional LAN board.
CPU embeds the 10/100 PHY MAC address.
The maximum access speed is 100 Mbps.
When the system is connected to LAN, the system detects the speed automatically
(Auto Nego).
Remote Monitoring function via Ethernet
PHY uses LXT972 and operates in 10/100 Mbps Full Duplex
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