Auxiliary Area Data Allocation; Auxiliary Area Flags And Bits For Built-In Inputs - Omron CJ1M-CPU21 Operation Manual

Auxiliary Area Data Allocation

4-3 Auxiliary Area Data Allocation
4-3-1

Auxiliary Area Flags and Bits for Built-in Inputs

Interrupt Inputs
Name Address
Interrupt Counter 0 A532
Counter SV
Interrupt Counter 1 A533
Counter SV
Interrupt Counter 2 A534
Counter SV
Interrupt Counter 3 A535
Counter SV
Interrupt Counter 0 A536
Counter PV
Interrupt Counter 1 A537
Counter PV
Interrupt Counter 2 A538
Counter PV
Interrupt Counter 3 A539
Counter PV
High-speed Counters
Name Address
High-speed Counter A270 to
0 PV A271
High-speed Counter A272 to
1 PV A273
68
The following tables show the Auxiliary Area words and bits that are related to
the CJ1M CPU Unit's built-in inputs. These allocations apply to CPU Units
equipped with the built-in I/O functions only.
Description
Used for interrupt input 0 in counter mode.
Sets the count value at which the interrupt task
will start. Interrupt task 140 will start when inter-
rupt counter 0 has counted this number of
pulses.
Used for interrupt input 1 in counter mode.
Sets the count value at which the interrupt task
will start. Interrupt task 141 will start when inter-
rupt counter 1 has counted this number of
pulses.
Used for interrupt input 2 in counter mode.
Sets the count value at which the interrupt task
will start. Interrupt task 142 will start when inter-
rupt counter 2 has counted this number of
pulses.
Used for interrupt input 3 in counter mode.
Sets the count value at which the interrupt task
will start. Interrupt task 143 will start when inter-
rupt counter 3 has counted this number of
pulses.
These words contain the interrupt counter PVs
for interrupt inputs operating in counter mode.
In increment mode, the counter PV starts incre-
menting from 0. When the counter PV reaches
the counter SV, the PV is automatically reset to
0.
In decrement mode, the counter PV starts dec-
rementing from the counter SV. When the
counter PV reaches the 0, the PV is automati-
cally reset to the SV.
Description
Contains the PV of high-speed counter 0. A271
contains the leftmost 4 digits and A270 contains
the rightmost 4 digits.
Contains the PV of high-speed counter 1. A273
contains the leftmost 4 digits and A272 contains
the rightmost 4 digits.
Section 4-3
Read/Write Times when data is
accessed
Read/Write • Retained when
power is turned
ON.
• Retained when
operation starts.
Read/Write
Read/Write
Read/Write
Read/Write • Retained when
power is turned
ON.
Read/Write
• Cleared when
operation starts.
Read/Write
• Refreshed when
interrupt is gener-
ated.
Read/Write
• Refreshed when
INI(880) instruc-
tion is executed.
Read/Write Times when data is
accessed
Read only • Cleared when
power is turned
ON.
• Cleared when
Read only
operation starts.
• Refreshed each
cycle during over-
seeing process.
• Refreshed when
PRV(881) instruc-
tion is executed
for the corre-
sponding counter.