3.3 PILOT CHANNEL COMMUNICATIONS
d) RECEIVE TIMING
The RS422 interface utilizes NRZI-MARK modulation code and; therefore, does not rely on an Rx clock to recapture data.
NRZI-MARK is an edge-type, invertible, self-clocking code.
To recover the Rx clock from the data-stream, an integrated DPLL (digital phase lock loop) circuit is utilized. The DPLL is
driven by an internal clock, which is 16-times over-sampled, and uses this clock along with the data-stream to generate a
data clock that can be used as the SCC (serial communication controller) receive clock.
The two-channel two-clock RS422 interface (module 7V) is intended for use with the synchrophasor feature. The module
connections are illustrated below.
Figure 3–38: TWO-CHANNEL TWO-CLOCK RS422 INTERFACE CONNECTIONS
The following figure shows the combined RS422 plus fiberoptic interface configuration at 64K baud. The 7L, 7M, 7N, 7P,
and 74 modules are used in two-terminal with a redundant channel or three-terminal configurations where channel 1 is
employed via the RS422 interface (possibly with a multiplexer) and channel 2 via direct fiber.
AWG 20-24 twisted shielded pair is recommended for external RS422 connections and ground the shield only at one end.
For the direct fiber channel, address power budget issues properly.
Connections shown above are for multiplexers configured as DCE (data communications equipment) units.
When using a LASER Interface, attenuators can be necessary to ensure that you do not exceed
maximum optical input power to the receiver.
Figure 3–39: RS422 AND FIBER INTERFACE CONNECTION
L90 Line Current Differential System
3.3.6 TWO-CHANNEL TWO-CLOCK RS422 INTERFACE
3.3.7 RS422 AND FIBER INTERFACE