Each equation is evaluated in the order in which the parameters have been entered.
FlexLogic provides latches which by definition have a memory action, remaining in the set state after the set input
has been asserted. However, they are volatile; that is, they reset on the re-application of control power.
When making changes to settings, all FlexLogic equations are re-compiled whenever any new setting value is
entered, so all latches are automatically reset. If it is necessary to re-initialize FlexLogic during testing, for example,
it is suggested to power the unit down and then back up.
This section provides an example of implementing logic for a typical application. The sequence of the steps is quite impor-
tant as it should minimize the work necessary to develop the relay settings. Note that the example presented in the figure
below is intended to demonstrate the procedure, not to solve a specific application situation.
In the example below, it is assumed that logic has already been programmed to produce virtual outputs 1 and 2, and is only
a part of the full set of equations used. When using FlexLogic, it is important to make a note of each virtual output used – a
virtual output designation (1 to 96) can only be properly assigned once.
VIRTUAL OUTPUT 1
VIRTUAL OUTPUT 2
VIRTUAL INPUT 1
DIGITAL ELEMENT 1
DIGITAL ELEMENT 2
CONTACT INPUT H1c
Inspect the example logic diagram to determine if the required logic can be implemented with the FlexLogic operators.
If this is not possible, the logic must be altered until this condition is satisfied. Once this is done, count the inputs to
each gate to verify that the number of inputs does not exceed the FlexLogic limits, which is unlikely but possible. If the
number of inputs is too high, subdivide the inputs into multiple gates to produce an equivalent. For example, if 25
inputs to an AND gate are required, connect Inputs 1 through 16 to AND(16), 17 through 25 to AND(9), and the outputs
from these two gates to AND(2).
Inspect each operator between the initial operands and final virtual outputs to determine if the output from the operator
is used as an input to more than one following operator. If so, the operator output must be assigned as a virtual output.
For the example shown above, the output of the AND gate is used as an input to both OR#1 and Timer 1, and must
therefore be made a virtual output and assigned the next available number (i.e. Virtual Output 3). The final output must
also be assigned to a virtual output as virtual output 4, which will be programmed in the contact output section to oper-
ate relay H1 (that is, contact output H1).
Figure 5–49: EXAMPLE LOGIC SCHEME
L90 Line Current Differential System
5.5.3 FLEXLOGIC EVALUATION
5.5.4 FLEXLOGIC EXAMPLE