Table of Contents
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Name
Logic.LE66.Timer Out
Logic.LE66.Out
Logic.LE66.Out inverted
Logic.LE66.Gate In1-I
Logic.LE66.Gate In2-I
Logic.LE66.Gate In3-I
Logic.LE66.Gate In4-I
Logic.LE66.Reset Latch-I
Logic.LE67.Gate Out
Logic.LE67.Timer Out
Logic.LE67.Out
Logic.LE67.Out inverted
Logic.LE67.Gate In1-I
Logic.LE67.Gate In2-I
Logic.LE67.Gate In3-I
Logic.LE67.Gate In4-I
Logic.LE67.Reset Latch-I
Logic.LE68.Gate Out
Logic.LE68.Timer Out
Logic.LE68.Out
Logic.LE68.Out inverted
Logic.LE68.Gate In1-I
Logic.LE68.Gate In2-I
Logic.LE68.Gate In3-I
Logic.LE68.Gate In4-I
Logic.LE68.Reset Latch-I
Logic.LE69.Gate Out
Logic.LE69.Timer Out
Logic.LE69.Out
Logic.LE69.Out inverted
Logic.LE69.Gate In1-I
Logic.LE69.Gate In2-I
Logic.LE69.Gate In3-I
Logic.LE69.Gate In4-I
Logic.LE69.Reset Latch-I
Logic.LE70.Gate Out
Logic.LE70.Timer Out
Description
Signal: Timer Output
Signal: Latched Output (Q)
Signal: Negated Latched Output (Q NOT)
State of the module input: Assignment of the Input Signal
State of the module input: Assignment of the Input Signal
State of the module input: Assignment of the Input Signal
State of the module input: Assignment of the Input Signal
State of the module input: Reset Signal for the Latching
Signal: Output of the logic gate
Signal: Timer Output
Signal: Latched Output (Q)
Signal: Negated Latched Output (Q NOT)
State of the module input: Assignment of the Input Signal
State of the module input: Assignment of the Input Signal
State of the module input: Assignment of the Input Signal
State of the module input: Assignment of the Input Signal
State of the module input: Reset Signal for the Latching
Signal: Output of the logic gate
Signal: Timer Output
Signal: Latched Output (Q)
Signal: Negated Latched Output (Q NOT)
State of the module input: Assignment of the Input Signal
State of the module input: Assignment of the Input Signal
State of the module input: Assignment of the Input Signal
State of the module input: Assignment of the Input Signal
State of the module input: Reset Signal for the Latching
Signal: Output of the logic gate
Signal: Timer Output
Signal: Latched Output (Q)
Signal: Negated Latched Output (Q NOT)
State of the module input: Assignment of the Input Signal
State of the module input: Assignment of the Input Signal
State of the module input: Assignment of the Input Signal
State of the module input: Assignment of the Input Signal
State of the module input: Reset Signal for the Latching
Signal: Output of the logic gate
Signal: Timer Output
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EMR-4000
IM02602009E
952
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