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Name
Logic.LE20.Reset Latch-I
Logic.LE21.Gate Out
Logic.LE21.Timer Out
Logic.LE21.Out
Logic.LE21.Out inverted
Logic.LE21.Gate In1-I
Logic.LE21.Gate In2-I
Logic.LE21.Gate In3-I
Logic.LE21.Gate In4-I
Logic.LE21.Reset Latch-I
Logic.LE22.Gate Out
Logic.LE22.Timer Out
Logic.LE22.Out
Logic.LE22.Out inverted
Logic.LE22.Gate In1-I
Logic.LE22.Gate In2-I
Logic.LE22.Gate In3-I
Logic.LE22.Gate In4-I
Logic.LE22.Reset Latch-I
Logic.LE23.Gate Out
Logic.LE23.Timer Out
Logic.LE23.Out
Logic.LE23.Out inverted
Logic.LE23.Gate In1-I
Logic.LE23.Gate In2-I
Logic.LE23.Gate In3-I
Logic.LE23.Gate In4-I
Logic.LE23.Reset Latch-I
Logic.LE24.Gate Out
Logic.LE24.Timer Out
Logic.LE24.Out
Logic.LE24.Out inverted
Logic.LE24.Gate In1-I
Logic.LE24.Gate In2-I
Logic.LE24.Gate In3-I
Logic.LE24.Gate In4-I
Logic.LE24.Reset Latch-I
Description
State of the module input: Reset Signal for the Latching
Signal: Output of the logic gate
Signal: Timer Output
Signal: Latched Output (Q)
Signal: Negated Latched Output (Q NOT)
State of the module input: Assignment of the Input Signal
State of the module input: Assignment of the Input Signal
State of the module input: Assignment of the Input Signal
State of the module input: Assignment of the Input Signal
State of the module input: Reset Signal for the Latching
Signal: Output of the logic gate
Signal: Timer Output
Signal: Latched Output (Q)
Signal: Negated Latched Output (Q NOT)
State of the module input: Assignment of the Input Signal
State of the module input: Assignment of the Input Signal
State of the module input: Assignment of the Input Signal
State of the module input: Assignment of the Input Signal
State of the module input: Reset Signal for the Latching
Signal: Output of the logic gate
Signal: Timer Output
Signal: Latched Output (Q)
Signal: Negated Latched Output (Q NOT)
State of the module input: Assignment of the Input Signal
State of the module input: Assignment of the Input Signal
State of the module input: Assignment of the Input Signal
State of the module input: Assignment of the Input Signal
State of the module input: Reset Signal for the Latching
Signal: Output of the logic gate
Signal: Timer Output
Signal: Latched Output (Q)
Signal: Negated Latched Output (Q NOT)
State of the module input: Assignment of the Input Signal
State of the module input: Assignment of the Input Signal
State of the module input: Assignment of the Input Signal
State of the module input: Assignment of the Input Signal
State of the module input: Reset Signal for the Latching
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EMR-4000
IM02602009E
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