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Name
Statistics.ResFc I Demand
Statistics.ResFc P Demand
Statistics.ResFc Max
Statistics.ResFc Min
Statistics.StartFc I Demand-I
Statistics.StartFc P Demand-I
Logic.LE1.Gate Out
Logic.LE1.Timer Out
Logic.LE1.Out
Logic.LE1.Out inverted
Logic.LE1.Gate In1-I
Logic.LE1.Gate In2-I
Logic.LE1.Gate In3-I
Logic.LE1.Gate In4-I
Logic.LE1.Reset Latch-I
Logic.LE2.Gate Out
Logic.LE2.Timer Out
Logic.LE2.Out
Logic.LE2.Out inverted
Logic.LE2.Gate In1-I
Logic.LE2.Gate In2-I
Logic.LE2.Gate In3-I
Logic.LE2.Gate In4-I
Logic.LE2.Reset Latch-I
Logic.LE3.Gate Out
Logic.LE3.Timer Out
Logic.LE3.Out
Logic.LE3.Out inverted
Logic.LE3.Gate In1-I
Logic.LE3.Gate In2-I
Logic.LE3.Gate In3-I
Logic.LE3.Gate In4-I
Logic.LE3.Reset Latch-I
Logic.LE4.Gate Out
Logic.LE4.Timer Out
Logic.LE4.Out
Logic.LE4.Out inverted
Description
Signal: Resetting of Statistics - Current Demand (avg, peak avg)
Signal: Resetting of Statistics - Power Demand (avg, peak avg)
Signal: Resetting of all Maximum values
Signal: Resetting of all Minimum values
State of the module input: Start of Statistics of the Current Demand (Update the displayed Demand )
State of the module input: Start of Statistics of the Active Power Demand
Signal: Output of the logic gate
Signal: Timer Output
Signal: Latched Output (Q)
Signal: Negated Latched Output (Q NOT)
State of the module input: Assignment of the Input Signal
State of the module input: Assignment of the Input Signal
State of the module input: Assignment of the Input Signal
State of the module input: Assignment of the Input Signal
State of the module input: Reset Signal for the Latching
Signal: Output of the logic gate
Signal: Timer Output
Signal: Latched Output (Q)
Signal: Negated Latched Output (Q NOT)
State of the module input: Assignment of the Input Signal
State of the module input: Assignment of the Input Signal
State of the module input: Assignment of the Input Signal
State of the module input: Assignment of the Input Signal
State of the module input: Reset Signal for the Latching
Signal: Output of the logic gate
Signal: Timer Output
Signal: Latched Output (Q)
Signal: Negated Latched Output (Q NOT)
State of the module input: Assignment of the Input Signal
State of the module input: Assignment of the Input Signal
State of the module input: Assignment of the Input Signal
State of the module input: Assignment of the Input Signal
State of the module input: Reset Signal for the Latching
Signal: Output of the logic gate
Signal: Timer Output
Signal: Latched Output (Q)
Signal: Negated Latched Output (Q NOT)
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EMR-4000
IM02602009E
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