Chipset; Gmch (815E Chipset) - Kontron speedMOPSlcdCE User Manual

KONTRON

Chipset

5.2
The chipset of the speedMOPSlcdCE consists of the Intel
Controller Hub) and the Intel

GMCH (815E Chipset)

5.2.1.
 Processor/Host Bus Support
 Intel® Pentium® III processor and Intel® Celeron®
 Supports processor's 370-Pin Socket
 Supports 32-Bit System Bus Addressing
 4 deep in-order queue; 4 or 1 deep request queue
 In-order and Dynamic Deferred Transaction Support
 66/100/133MHz System Bus Frequency
 GTL+ I/O Buffer
 Integrated SDRAM Controller
 32MB to 512MB using 16Mb/64Mb/128Mb/256Mb technology
 64-bit data interface
 100/133MHz system memory bus frequency
 Support for Asymmetrical SDRAM addressing only
 Support for x8 and x16 SDRAM device width
 Unbuffered, non-ECC SDRAM only supported
 Refresh Mechanism: CBR ONLY supported
 Enhanced Open page arbitration SDRAM paging scheme
 Integrated Graphics Controller
 3D Hyper Pipelined Architecture
 Full 2D H/W Acceleration
 Motion Video Acceleration
 Mip Maps with Trilinear and Anisotropic Filtering
 85MHz Flat-Panel Monitor/Digital CRT Interface Or Digital Video
 Integrated 24-bit 230MHz RAMDAC
 Gamma Corrected Video
 DDC2B Compliant
 Up to 1600x1200 in 8-bit Color at 85Hz Refresh
 Hardware Accelerated Functions
 3 Operand Raster Bit BLTs
 64x64x3 Color Transparent Cursor

Power-Management Functions
 Stop Clock Grant and Halt special cycle translation from the host to the hub interface
 APM compliant power management
speedMOPSlcdCE User's Guide
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82801DB ICH-4 (I/O Controller Hub 4).
15
815E chipset GMCH (Graphics and Memory
CPU, Chipset and Super I/O