Philips DVDR615 Service Manual page 138

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EN 138 9.
Clock Distribution
24.576 MHz
7007
VIP7118
7001
1394 LINK
7000
1394 PHY
24.576 MHz
The Chrysalis [7800] has a complex clock system, which is
needed to support the processes running at different
frequencies such as video decoding, audio decoding or
peripheral I/O devices etc. To ensure a synchronous
initialization of all the registers and state machines, all the PLLs
are switched to their default frequency and the reset sequence
is run at 4MHz. Then when the booting control unit is correctly
initialized and once it has captured all the booting parameters,
it sets the PLLs to its functional frequency to allow the modules
to run at their nominal frequencies. Thanks to a clock blocking
mechanism, the frequency switching is glitch free.
System clocks:
• PNX7100 [7800], pins AF9 and AF10 : 4MHz provided by
the crystal oscillator [7804]
• SAA7118 [7007], pins A3 and B4 : 24.576 MHz provided by
crystal [1002]
3V3dig
7926
NCP303
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DVDR615/69 Circuit-, IC descriptions and list of abbreviations
7800
7924
AUDIO PLL
Figure 9-6 Chrysalis Clock
7800
>1
PNX7100_Resetn
Figure 9-7 Chrysalis reset
FRONTEND INTERFACE
CHRYSALIS
PNX7100
4 MHz
• SDRAM [7902] and [7903], pin 38 : 133MHz provided by
PNX7100
• 1394-LINK [7001], pin 88 : 49.152MHz provided by 1394-
PHY
• 1394-PHY [7000], pin 59 and 60 : 24.576MHz provided by
crystal [1001]
Memory
Several memories are used on the Chrysalis [7800]:
• EEPROM [7904] : this memory contains all the necessary
boot parameters of the board
• EEPROM [7905] : this memory contains all the necessary
parameters for the application
• FLASH [7900] : this memory contains the application,
diagnosis and service software
Reset
CHRYSALIS
GPIO
PNX7100
PNX7100_SYS_Resetn
7902
133MHz
SDRAM
7903
SDRAM
3V3dig
Reset_IDEn
7923-1
&
Reset_1394n
7923-4
&
Analog_Reset
7923-2
&
VIP_Resetn
7923-3
&
CL 36532004_005.eps
140203