Philips DVDR615 Service Manual page 133

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Circuit-, IC descriptions and list of abbreviations DVDR615/69 9. EN 133
The sound processing is always done in stereo (that means
separate left- and right-channel).
a) Record path:
The complete selection of audio signal for recording is done by
a HEF4052 [7501], which is a dual four-to-one multiplexer. The
input lines for the selector [7501] are coming either from MSP
[7600] (AFEL / AFER) or cinch rear-in Ext 1 (AIN1L / AIN1R) or
cinch rear-in Ext 2 (AIN2L / AIN2R) or the cinch front-in (AINFL
/ AINFR). The [7501] is controlled via RSA1- and RSA2-signals
coming from the MSP [7600]. The MSP acts as a port expander
of the slave µP. The Op-Amp on the output [7500] is necessary
for performance reasons and acts also as a driver. The
selected signals ALADC and ARADC are directly fed to the
Audio-ADC.
As there is also a fifth input (DV-in), the corresponding audio
signals ALDAC / ARDAC) from the FEBE board are routed via
the MSP [7600] and output as AFEL / AFER to selector 7501
b) Line-out path:
See chapter 9.1.12
c) Digital audio-out path:
In addition to the analog output the set is also equipped with a
digital audio output via cinch plug [1955]. The signal is
generated on the FEBE board and routed via the audio
interface cable and connector [1900] to the MOBO (Analog)
board. Here the DAOUT-line first passes a 6-fold inverter
[7551] being used as a driver and for performance reasons
(noise reduction, jitter, etc.). Afterwards a transformer [5551] is
necessary to achieve the correct level and also to have a
floating output with isolated ground before the signal is fed via
[3559 & 3563] to cinch plug [1955]. The capacitor [2553]
performs an AC-coupling between connector- and set-ground.
9.1.12 Audio ADC/DAC
The conversion of analog audio signals from the record-
selector [7501] in the I/O (ALADC- & ARADC-) is done via
UDA1361TS [7006]. This IC can process input signals up to
2Vrms by using external resistors [3029, 3030] in series to the
input pins. All required clock signals are generated on the
FEBE board and only the audio data (A_DAT-line) are routed
from MOBO (Analog) to FEBE board for further processing.
The transformation of digital audio back into the analog domain
is done by UDA1334BTS [7001]. All necessary clock signals
are coming from the FEBE board and digital audio data
(D_DATA0-line) are converted into analog signals, which are
available at pins 14 and 16 of [7001]. Afterwards an Op-
Amplifier [7003] (line driver & level adaptation, gain = 2), which
also works as low-pass filter to increase signal performance
(noise, distortions,), is passed. Then both signals (ALDAC &
ARDAC) are directly routed to the rear cinch output. The DAC
has also a mute possibility, which can be activated by setting
pin 8 to 3.3V via [7002]. This mute is controlled either by the
FEBE board (D_KILL-line) or IMUTE from the slave µP or the
IPFAIL-signal from the Power Supply Unit.
The signals from the audio DAC part (ARDAC/ALDAC) are
directly routed to both cinch rear outputs, which are connected
in parallel. To avoid plops and any other audible noise on the
output there is a mute-stage implemented [7503 & 7504] for
each channel. The activation is done via AKILL-line, which is
a combination of the KILL from the IMUTE from slave µP,
D_KILL from FEBE board, DAC_MUTE from DAC-part and
IPFAIL from the Power supply unit.
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