Philips DVDR615 Service Manual page 113

Circuit Diagrams and PWB Layouts
FEBE: BE DV In IEEE1394
1 2 3
+3V3_IEEE_A
A
52 51 42
3018
AVDD
10K
B OPTION
3019
F001 40
R0
6K34
1% F003 BIAS
41
R1
VOLTAGE
2003 F004
38 TPBIAS0
AND
1u0 CURRENT
GENERATOR
37
TPA0+
1000
SR
36
C TPA0-
7 8 F006
6
F008
5
F010
4
35 TPB0+
3
F014
2
34 TPB0-
F017
1
59
F047 XI
XTAL OSC.
60
D F029 XO
PLL
CLOCK
16
43
4009
1394_CLK TRANSMIT
44
OPTION
DATA
45 ENCODER
1001
3016 NC
46
1R0
47
CX-11F
24M576
2007
54
E
PDI1394P25
100n 2008
55
100n
OPTION
28 29 50 49 48
F
5000
F038
+3V3_IEEE_PLL
G
5001
F043
+3V3_IEEE_A
H
5002
F045
+3V3_IEEE_D
+3V3dig
I
OPTIONAL FOR 3104 128 0927
1 2 3
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DVDR615/69
4 5 6
+3V3_IEEE_D +3V3_IEEE_PLL +3V3_IEEE_D +3V3_IEEE_D
2000
1n0
7000
27 62 61 26 25 56
31 30
PDI1394P25
TESTM PLLVDD
DVDD
24
CPS
15 F002
LPS
RECEIVED
23
DATA ISO_ +3V3_IEEE_D
DECODER/
F005
C|LKON 19
TIMER
SYSCLK 2
LREQ 1
3023
4
LINK CTL0
INTERFACE
10R 3024
5
CTL1
10R
3025-1
6
D0 8 1
10R
3025-2
D1 7 7 2
10R
3025-3 3
D2 8 6
ARBITR'N
AND 10R
9 3025-4 4
D3 5
CONTROL
10R
STATE 10 3029-1 1
D4 8
MACHINE
10R 3029-2
11
D5 7 2
LOGIC
10R
3029-3
12
D6 6 3
10R
3029-4
13
D7 5 4
10R
3030
PC0 20
10R
3034
PC1 21
3035 22R
22
PC2
+3V3_IEEE_D
10K
3 F036
CNA 4001
MPIO8_1394_CNA
53 F037
RESET_ 4002
14
PD
AGND DGND PLLGND
39 33 32 64 63 18 17 58 57
PHY
PCI_AD(31:0)
+3V3_LINK
MPIO2_1394_IRQn
F046
+3V3_LINK
4 5 6
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7. EN 113
7 8 9 10
+3V3_IEEE_D +3V3_LINK
3038
F000
1R0
+3V3_LINK
3039
1R0
OPTION
VDD
F007
82 PHYD0
81 PHYD1
F011
80 PHYD2
79 PHYD3
F015
76 PHYD4
75 PHYD5
F019 12KB BUFFER
74 PHYD6
73 PHYD7 MEMORY
F022
86 PHYCTL0
85 PHYCTL1
LINK
F025
87 LREQ ISOCH & ASYNC
CORE
88 SCLK
F028 PACKETS
91 LPS
56 CYCLEIN
F032 F033
57 CYCLEOUT
55 CLK50
47 1394MODE
48 PD
92 LINKON
93 ISON
+3V3_LINK
42 RESET_
RESET_1394n
CONTROL
AND
49
STATUS
1
50
2 REGISTERS
51
3
52
4
58
5
59
6
72
7
71
8 ASYNC
104
9
TRANSMITTER
65
10
66 AND
11
67
RECEIVER
12
68
13
105
14
129
15
144
16
130
17
PCI_AD(24) 3010-4 4 5 220R 22 HIFAD0
PCI_AD(25) 3010-3 3 6 220R 21 HIFAD1
PCI_AD(26) 3010-2 2 7 220R 20 HIFAD2
PCI_AD(27) 3010-1 1 8 220R 19 HIFAD3
PCI_AD(28)
3009-4 4 5 220R 16 HIFAD4
PCI_AD(29)
3009-3 3 6 220R 15 HIFAD5
PCI_AD(30)
3009-2 2 7 220R 14 HIFAD6
PCI_AD(31)
3009-1 1 8 220R 13 HIFAD7
8-BIT
3008-1 8 1 4K7 10 HIFD8
3008-2 7 2 4K7 9 HIFD9
3008-3 6 3 4K7 8 HIFD10 INTERFACE
3008-4 5 4 4K7 7 HIFD11
3007-1 8 1 4K7 4 HIFD12
3007-2 7 2 4K7 3 HIFD13
3007-3 6 3 4K7 2 HIFD14
3007-4 5 4 4K7 1 HIFD15
F042 38 HIFINT_
41 HIFWAIT
33R 3060
GND
F044
+3V3_LINK
7 8 9 10
11 12 13
LINK
7001
PDI1394L40
108
AV1D0 3000-4 4 5 33R F009 L_D(0)
AV1D1 109 3000-3 3 6 33R F012 L_D(1)
AV1D2 110 3000-2 2 7 F013 L_D(2)
33R
AV1D3 111 3000-1 1 8 F016 L_D(3)
33R
AV1D4 114 3001-4 4 5 F018 L_D(4)
33R
AV1D5 115 3001-3 3 6 F020 L_D(5)
33R
AV1D6 116 3001-2 2 7 F021 L_D(6)
33R
AV1D7 117 3001-1 1 8 33R F023 L_D(7)
AV1CLK 99 3002 33R F024 L_CLK
AV1FSYNC 100 3026 33R F026 L_FSYNC
L_VAL
AV1VALID 102 3027 33R F027
AV1SY 101 F030 3046 10K
103 L_SYNC
AV1SYNC 3028 33R F031
98
AV1ENDPCK F034 3047 10K
96
AV1ERR0
AV1ERR1 97
3045
AV1READY 118 F035
+3V3_LINK
10K
AV2D0 133 3003-4 4 5 33R MX_D(0)
AV2D1 134 3003-3 3 6 33R MX_D(1)
AV2D2 135 3003-2 2 7 33R MX_D(2)
AV2D3 136 3003-1 1 8 33R MX_D(3)
139
AV2D4 3004-4 4 5 33R MX_D(4)
AV2D5 140 3004-3 3 6 MX_D(5)
33R
AV2D6 141 3004-2 2 7 MX_D(6)
33R
AV2D7 142 3004-1 1 8 MX_D(7)
33R
AV2CLK 124 MX_CLK
3048 33R
AV2FSYNC 125
3051 4K7
AV2VALID 127 MX_VAL
3049 33R
AV2SY 126 3052 4K7
AV2SYNC 128 3050 33R MX_SYNC
AV2ENDPCK 123 3053 4K7
AV2ERR0|LTLEND 121 3054 22K
AV2ERR1|DATINV 122 3055 22K
143
AV2READY 3056 4K7 +3V3_LINK
62
1
63
TESTPIN 2
64
3
HIFA0 33 3005-1 1 8 220R PCI_AD(0)
HIFA1 32 3005-2 2 7 220R PCI_AD(1)
PCI_AD(2)
HIFA2 31 3005-3 3 6 220R
PCI_AD(3)
HIFA3 30 3005-4 4 5 220R
PCI_AD(4)
HIFA4 29 3006-1 1 8 220R
PCI_AD(5)
HIFA5 28 3006-2 2 7 220R
27 PCI_AD(6)
HIFA6 3006-3 3 6 220R
HIFA7 26 3006-4 4 5 220R PCI_AD(7)
HIFA8 25 100R PCI_AD(8)
3011
HIFSC_ 36
F039 3057 100R
XIO_SEL1
HIFWR_ 37
F040 3058 100R
PCI_CBE(1)
HIFALE 39
HIFRD_ 40
F041 3059 100R
PCI_CBE(2)
HIF16BIT 45
HIFMUX 46 4003
+3V3_LINK
OPTION
4004
+3V3_LINK
F029 IC7000 pin 60
11 12 13
14
1000 C1 3046 D13
1001 E1
3047 D13
2000 A5 3048 E12
2001 B8 3049 E12
L_D(7:0) 2002 B6 3050 F12
2003 B2 3051 E12
L_D_CTL
2004 D1 3052 F12
2005 E1 3053 F12
MX_D(7:0)
2006 E1 3054 F12
2007 E2 3055 F12
MX_D_CTL
2008 E2 3056 F11
PCI_AD(31:0)
2009 G2 3057 G12
A 2010 H2 3058 G12
2011 H2 3059 G12
2012 H2 3060 H8
2013 H3 4000 A4
2014 I1 4001 E6
2015 I2 4002 E6
2016 I2 4003 G12
2017 I4 4004 H12
2018 I5 4009 D1
2019 I5 5000 G1
2020 I5 5001 G1
2021 I6 5002 H1
B
2022 I6 7000 B5
2023 I6 7001 C11
2024 I6 F000 B8
2025 I7 F001 B3
2026 I7 F002 B5
2027 I7 F003 B3
2028 I8 F004 B3
2029 I8 F005 B5
2030 I8 F006 C1
2031 I8 F007 C7
2032 I9 F008 C1
2033 I9 F009 C12
C
2034 I9 F010 C1
3000-1 C12 F011 C7
3000-2 C12 F012 C12
3000-3 C12 F013 C12
3000-4 C12 F014 C1
3001-1 D12 F015 C7
3001-2 D12 F016 C12
3001-3 D12 F017 C1
3001-4 C12 F018 C12
3002 D12 F019 C7
3003-1 E12 F020 D12
D 3003-2 E12 F021 D12
3003-3 E12 F022 D7
3003-4 E12 F023 D12
3004-1 E12 F024 D12
3004-2 E12 F025 D7
3004-3 E12 F026 D12
3004-4 E12 F027 D12
3005-1 F12 F028 D7
3005-2 G12 F029 D2
3005-3 G12 F030 D12
3005-4 G12 F031 D12
3006-1 G12 F032 D7
E
3006-2 G12 F033 D8
3006-3 G12 F034 D12
3006-4 G12 F035 D12
3007-1 G8 F036 E5
3007-2 G8 F037 E5
3007-3 G8 F038 G2
3007-4 G8 F039 G12
3008-1 G8 F040 G12
3008-2 G8 F041 G12
3008-3 G8 F042 G8
3008-4 G8 F043 H2
3009-1 G8 F044 H10
F
3009-2 G8 F045 H2
3009-3 G8 F046 I5
3009-4 G8 F047 D1
3010-1 G8
3010-2 F8
3010-3 F8
3010-4 F8
3011 G12
3012 H13
3013 D1
3014 D2
G 3015 D2
3016 E2
3017 F3
3018 B2
3019 B2
3020 C2
3021 C2
3022 B5
3023 C6
3024 C7
3025-1 C6
3025-2 C7
H
3025-3 C6
3025-4 C7
3026 D12
3027 D12
3028 D12
3029-1 D6
3029-2 D7
3029-3 D6
3029-4 D7
3030 D6
3034 D7
3035 D6
I
3036 B7
3037 B7
3038 B7
3039 B7
3040 B8
3041 B7
3042 B7
TR20043_001.eps 3043 B8
3044 E5
14062004
3045 D12
14