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PREPARATION FOR USE
2-31.
MULTIBUS PRIORITY RESOLUTION
The iSBC 86/14/30 board is designed to be a "full master" board on the
Multibus interface.
That is, the board is equipped with bus arbitration
logic that can acquire and release control of the Multibus interface.
In
order for the board to interact effectively in your system, you must
enable the board priority scheme by configuring the BPRO/ and BPRN/
signals on the Multibus interface.
If the iSBC 86/14/30 board is the only bus master in the system (the only
board capable of controlling the Multibus interface control signals),
install it into the top-most cardcage slot (slot J2 on the iSBC 604/614
cardcage) or into any slot that contains a jumper connecting BPRN/ to
ground.
If there are more bus masters in your system, you must configure a
priority scheme for accessing the shared resources in the system.
The
two priority methods available, serial and parallel, are described in the
following paragraphs.
NOTE
If your system includes more than one
bus master, ensure that the BCLK/ and
CCLK/ signals are generated on
theMultibus interface by only one bus
master.
All bus masters contain
provisions for disabling the BCLK/ and
CCLK/ signals to the Multibus interface.
2-32.
Serial Priority Resolution
Serial priority resolution is implemented by arranging the board sequence
in the cardcage slots.
The top priority board must be installed into
cards Ito J2 (in an iSBC 604/614 Cardcage).
The next hghest priority
board must be installed into card slot J3, and card slot J4 contains the
lowest priority board in the system.
Due to the propogation delays on
the BPRo/ signal, this priority scheme is limited to containing up to 3
bus master boards.
Figure 2-9 shows a serial priority configuration
example in which the iSBC 604/614 cardcage is used and the highest
priority master is installed into cards lot J2.
NOTE
The top priority card slot is the only
one in this priority scheme that
connects the BPRN/ signal to ground on
the backplane.
2-62
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