Errata - Intel SL3QA - Pentium III 550 MHz Processor Specification

Errata

Errata
E1. FP Data Operand Pointer May Be Incorrectly Calculated After FP
Access Which Wraps 64 Kbyte Boundary in 16 Bit Code
Problem: The FP Data Operand Pointer is the effective address of the operand associated with
the last non-control floating-point instruction executed by the machine. If an 80-bit
floating-point access (load or store) occurs in a 16-bit mode other than protected
mode (in which case the access will produce a segment limit violation), the memory
access
subsequently saved, the value contained in the FP Data Operand Pointer may be
incorrect.
Implication: A 32-bit operating system running 16-bit floating-point code may encounter this
erratum, under the following conditions:
• The operating system is using a segment greater than 64 Kbytes in size.
• An application is running in a 16-bit mode other than protected mode.
• An 80-bit floating-point load or store which wraps the 64-Kbyte boundary is
executed.
• The
(FSAVE/FNSAVE/FSTENV/FNSTENV) after the above memory access.
• The operating system uses the value contained in the FP Data Operand Pointer.
Wrapping an 80 bit floating-point load around a segment boundary in this way is not
a normal programming practice. Intel has not currently identified any software which
exhibits this behavior.
Workaround: If the FP Data Operand Pointer is used in an OS which may run 16-bit floating-
point code, care must be taken to ensure that no 80-bit floating-point accesses are
wrapped around a 64-Kbyte boundary
Status: For the steppings affected see the Summary of Changes at the beginning of this
section.
E2. Differences Exist in Debug Exception Reporting
Problem: There exist some differences in the reporting of code and data breakpoint matches
between that specified by previous Intel processor specifications and the behavior of
the processor, as described below:
Case 1: The first case is for a breakpoint set on a MOVSS or POPSS instruction, when
Specification Update
wraps a 64-Kbyte
operating system
the instruction following it causes a debug register protection fault (DR7.gd
is already set, enabling the fault). The processor reports delayed data
breakpoint matches from the MOVSS or POPSS instructions by setting the
matching DR6.bi bits, along with the debug register protection fault
boundary, and the floating-point environment is
performs a floating-point environment store
39