Intel SL3QA - Pentium III 550 MHz Processor Specification page 43

Errata
Note that even if this combination of instructions is encountered, there is also a
dependency on the internal pipelining and execution state of both instructions in the
processor.
Implication: Inexact-result exceptions are commonly masked or ignored by applications, as it
happens frequently, and produces a rounded result acceptable to most applications.
The PE bit of the FPU status word may not always be set upon receiving an inexact-
result exception. Thus, if these exceptions are unmasked, a floating-point error
exception handler may not recognize that a precision exception occurred. Note that
this is a "sticky" bit, i.e., once set by an inexact-result condition, it remains set until
cleared by software.
Workaround: This condition can be avoided by inserting two NOP instructions between the two
floating-point instructions.
Status: For the steppings affected see the Summary of Changes at the beginning of this
section.
E7. BTM for SMI Will Contain Incorrect FROM EIP
Problem: A system management interrupt (SMI) will produce a Branch Trace Message (BTM), if
BTMs are enabled. However, the FROM EIP field of the BTM (used to determine the
address of the instruction which was being executed when the SMI was serviced) will
not have been updated for the SMI, so the field will report the same FROM EIP as the
previous BTM.
Implication: A BTM which is issued for an SMI will not contain the correct FROM EIP, limiting the
usefulness of BTMs for debugging software in conjunction with System Management
Mode (SMM).
Workaround: None identified.
Status: For the steppings affected see the Summary of Changes at the beginning of this
section.
E8. I/O Restart in SMM May Fail After Simultaneous MCE
Problem: If an I/O instruction (IN, INS, REP INS, OUT, OUTS, or REP OUTS) is being executed,
and if the data for this instruction becomes corrupted, the Pentium III processor will
signal a machine check exception (MCE). If the instruction is directed at a device
which is powered down, the processor may also receive an assertion of SMI#. Since
MCEs have higher priority, the processor will call the MCE handler, and the SMI#
assertion will remain pending. However, upon attempting to execute the first
instruction of the MCE handler, the SMI# will be recognized and the processor will
attempt to execute the SMM handler. If the SMM handler is completed successfully, it
will attempt to restart the I/O instruction, but will not have the correct machine state,
due to the call to the MCE handler.
Implication: A simultaneous MCE and SMI# assertion may occur for one of the I/O instructions
above. The SMM handler may attempt to restart such an I/O instruction, but will have
corrupted state due to the MCE handler call, leading to failure of the restart and
shutdown of the processor.
Specification Update 43