Intel SL3QA - Pentium III 550 MHz Processor Specification page 57

Errata
E35. Transmission Error on Cache Read
Problem: During reads of the L2 cache, the processor may use certain L2 cache optimizations
that may result in a data transmission error
Implication: Data corruption caused by this erratum will result in unpredictable system behavior.
Workaround: It is possible for BIOS code to contain a workaround for this erratum.
Status: For the steppings affected see the Summary of Changes at the beginning of this
section.
E36. Potential Loss of Data Coherency During MP Data Ownership Transfer
Problem: In MP systems, processors may be sharing data in different cache lines, referenced
as line A and line B in the discussion below. When this erratum occurs (with the
following example given for a 2-way MP system with processors noted as 'P0' and
'P1'), P0 contains a shared copy of line B in its L1. P1 has a shared copy of Line A.
Each processor must manage the necessary invalidation and snoop cycles before that
processor can modify and source the results of any internal writes to the other
processor.
There exists a narrow timing window when, if P1 requests a coy of line B it may be
supplied by P0 in an Exclusive state which allows P1 to modify the contents of the line
with no further external invalidation cycles. In this narrow window P0 may also retire
instructions that use the original data present before P1 performed the modification
Implication: Multiprocessor or threaded application synchronization, required for low-level data
sharing, that is implemented via operating system provided synchronization
constructs are not affected by this erratum. Applications which rely upon the usage of
locked semaphores rather than memory ordering are also unaffected. Uniprocessor
systems are not affected by this erratum. If the erratum does occur one processor
may execute software with the stale data that was present from the previous shared
state rather than the data written more recently by another processor.
Workaround: Deterministic barriers beyond which program variables will not be modified can
be achieved via the usage of locked semaphore operations. These should effectively
prevent the occurrence of this erratum
Status: For the steppings affected see the Summary of Changes at the beginning of this
section.
E37. Misaligned Locked Access to APIC Space Results in Hang
Problem: When the processor's APIC space is accessed with a misaligned locked access a
machine check exception is expected. However, the processor's machine check
architecture is unable to handle the misaligned locked access.
Implication: If this erratum occurs the processor will hang. Typical usage models for the APIC
address space do not use locked accesses. This erratum will not affect systems using
such a model.
Workaround: Ensure that all accesses to APIC space are aligned.
Specification Update 57