Intel SL3QA - Pentium III 550 MHz Processor Specification page 67

Errata
3. The register is then copied to an MMX™ technology register using the MOVD, or
converted to single precision floating-point and moved to an MMX technology
register using the CVTSI2SS instruction prior to any other operations on the sign-
extended value, or inserted into an MMX™ technology register using the PINSRW
instruction.
Specifically, the sign may be incorrectly extended into bits 16-31 of the MMX
technology register. In the case of the PINSRW instruction, a non-zero value could be
loaded into the MMX™ technology register. This erratum only affects the MMX™
technology register.
This erratum only occurs when the following three steps occur in the order shown.
This erratum may occur with up to 63 (39 for Pre-CPUID 0x6BX) intervening
instructions that do not modify the sign-extended value between steps 2 and 3.
1. XOR EAX, EAX
or SUB EAX, EAX
2. MOVSX AX, BL
or MOVSX AX, byte ptr <memory address> or MOVSX AX, BX
or MOVSX AX, word ptr <memory address> or IMUL BL (AX implicit, opcode F6
/5)
or IMUL byte ptr <memory address> (AX implicit, opcode F6 /5) or IMUL AX, BX
(opcode 0F AF /r)
or IMUL AX, word ptr <memory address> (opcode 0F AF /r) or IMUL AX, BX, 16
(opcode 6B /r ib)
or IMUL AX, word ptr <memory address>, 16 (opcode 6B /r ib) or IMUL AX, 8
(opcode 6B /r ib)
or IMUL AX, BX, 1024 (opcode 69 /r iw)
or IMUL AX, word ptr <memory address>, 1024 (opcode 69 /r iw)
or IMUL AX, 1024 (opcode 69 /r iw) or CBW
3. MOVD MM0, EAX or CVTSI2SS MM0, EAX
Note that the values for immediate byte/words are merely representative (i.e., 8, 16,
1024) and that any value in the range for the size is affected. Also, note that this
erratum may occur with "EAX" replaced with any 32-bit general-purpose register, and
"AX" with the corresponding 16-bit version of that replacement. "BL" or "BX" can be
Specification Update 67