Intel SL3QA - Pentium III 550 MHz Processor Specification page 62

Implication: This erratum may occur on a system with any number of processors. However, the
probability of occurrence increases with the number of processors. If this erratum
does occur, the system will hang with DBSY# asserted. At this point, the system
requires a hard reset.
Workaround: It is possible for BIOS code to contain a workaround for this erratum.
Status: For the steppings affected see the Summary of Changes at the beginning of this
section.
E47. Lower Bits of SMRAM SMBASE Register Cannot Be Written With an
ITP
Problem: The System Management Base (SMBASE) register (7EF8H) stores the starting
address of the System Management RAM (SMRAM). This register is used by the
processor when it is in System Management Mode (SMM), and its contents serve as
the memory base for code execution and data storage. The 32-bit SMBASE register
can normally be programmed to any value. When programmed with an In-Target
Probe (ITP), however, any attempt to set the lower 11 bits of SMBASE to anything
other than zeros via the WRMSR instruction will cause the attempted write to fail.
Implication: When set via ITP, any attempt to relocate SMRAM space must be made with 2-KB
alignment.
Workaround: None identified
Status: For the steppings affected see the Summary of Changes at the beginning of this
section.
E48. Task Switch Caused by Page Fault May Cause Wrong PTE and PDE
Access Bit to Be Set
Problem: If an operating system executes a task switch via a Task State Segment (TSS), and
the TSS is wholly or partially located within a clean page (A and D bits clear) and the
GDT entry for the new TSS is either misaligned across a cache line boundary or is in a
clean page, the accessed and dirty bits for an incorrect page table/directory entry
may be set.
Implication: An operating system which uses hardware task switching (or hardware task
management) may encounter this erratum. The effect of the erratum depends on
the alignment of the TSS and ranges from no anomalous behavior to unexpected
errors.
Workaround: The operating system could align all TSSs to be within page boundaries and set
the A and D bits for those pages to avoid this erratum. The operating system may
alternately use software task management.
Status: For the steppings affected see the Summary of Changes at the beginning of this
section.
E49. Unsynchronized
Unexpected Instruction Execution Results
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Cross-Modifying Code Operations
Errata
Can Cause
Specification Update