Intel SL3QA - Pentium III 550 MHz Processor Specification page 61

Errata
Problem: The Pentium III processor is designed to signal an unrecoverable Machine Check
Exception (MCE) as a consistency checking mechanism.
circumstances involving multiple speculative branches and memory accesses there
exists a one cycle long window in which the processor may signal a MCE in the
Instruction Fetch Unit (IFU) because instructions previously decoded have been
evicted from the IFU. The one cycle long window is opened when an opportunistic
fetch receives a partial hit on a previously executed but not as yet completed store
resident in the store buffer. The resulting partial hit erroneously causes the eviction
of a line from the IFU at a time when the processor is expecting the line to still be
present. If the MCE for this particular IFU event is disabled, execution will continue
normally.
Implication: While this erratum may occur on a system with any number of Pentium III
processors, the probability of occurrence increases with the number of processors. If
this erratum does occur, a machine check exception will result. Note systems that
implement an operating system that does not enable the Machine Check Architecture
will be completely unaffected by this erratum (e.g., Windows* 95 and Windows 98).
Workaround: It is possible for BIOS code to contain a workaround for this erratum.
Status: For the steppings affected see the Summary of Changes at the beginning of this
section.
E45. Performance
Prefetch
Problem: The processor allows the measurement of the frequency and duration of numerous
different internal and bus related events (see Intel Architecture Software Developer's
Manual, Volume 3, for more details).
architecture provides a mechanism to pre-load data into the L1 cache, bypassing the
L2 cache.
monitoring logic will incorrectly be included in the count of "L2_LINES_IN" (24H)
events and "L2_LINES_OUT" (26H) events.
Implication: If application software is run which utilizes the SSE L1 prefetch feature, the count of
"L2_LINES_IN" (24H) and "L2_LINES_OUT" (26H) will read a value that is greater
than the correct value.
Workaround: The correct value of "L2_LINES_IN" and "L2_LINES_OUT" may be calculated by
subtracting the value of the "MMX_PRE_MISS" (4BH) from each of these registers.
Status: For the steppings affected see the Summary of Changes at the beginning of this
section.
E46. Snoop Request May Cause DBSY# Hang
Problem: A small window of time exists in which a snoop request originating from a bus agent
to a processor with one or more outstanding memory transactions may cause the
processor to assert DBSY# without issuing a corresponding bus transaction, causing
the processor to hang (livelock). The exact circumstances are complex, and include
the relative timing of internal processor functions with the snoop request from a bus
agent
Specification Update
Counters Include
The number of these L1 pre-loads measured by the performance
Under a complex set of
Streaming SIMD
The Streaming SIMD Extension (SSE)
Extensions L1
61