Identification Information - Intel SL3QA - Pentium III 550 MHz Processor Specification

Identification Information

Component Identification via Programming Interface
The Pentium
Family
0110
0110
NOTES:
1.
2.
3.
The Pentium III processor's second level (L2) cache size can be determined by the
following register contents:
512-Kbyte Unified L2 Cache
256-Kbyte 8 way set associative
32byte line size, L2 Cache
512-Kbyte 8 way set associative
32byte line size, L2 Cache
NOTES:
1.
20
III processor can be identified by the following values:
®
1
The Family corresponds to bits [11:8] of the EDX register after RESET, bits [11:8] of
the EAX register after the CPUID instruction is executed with a 1 in the EAX register,
and the generation field of the Device ID register accessible through Boundary Scan.
The Model corresponds to bits [7:4] of the EDX register after RESET, bits [7:4] of the
EAX register after the CPUID instruction is executed with a 1 in the EAX register, and
the model field of the Device ID register accessible through Boundary Scan.
The Brand ID corresponds to bits [7:0] of the EBX register after the CPUID instruction is
executed with a 1 in the EAX register.
For the Pentium III processor, the unified L2 cache size corresponds to a token in the
EDX register after the CPUID instruction is executed with a 2 in the EAX register. Other
Intel microprocessor models or families may move this information to other bit positions
or otherwise reformat the result returned by this instruction; generic code should parse
the resulting token stream according to the definition of the CPUID instruction.
Model
2
0111
1000
1
1
1
Identification Information
Brand ID 3
00h = Not Supported
02h = "Intel ® Pentium ® III
Processor"
43h
82h
83h
Specification Update