Intel SL3QA - Pentium III 550 MHz Processor Specification page 71

Errata
E64. Cache Line Reads May Result in Eviction of Invalid Data
Problem: A small window of time exists in which internal timing conditions in the processor
cache logic may result in the eviction of an L2 cache line marked in the invalid state.
Implication: There are three possible implications of this erratum:
1. The processor may provide incorrect L2 cache line data by evicting an invalid line.
2. A BNR# (Block Next Request) stall may occur on the system bus.
3. Should a snoop request occur to the same cache line in a small window of time
the processor may incorrectly assert HITM#. It is then possible for an infinite
snoop stall to occur should another processor respond (correctly) to the snoop
request with HIT#. In order for this infinite snoop stall to occur, at least three
agents must be present, and the probability of occurrence increases with the
number of processors. Should 2 or 3 occur, the processor will eventually assert
BINIT# (if enabled) with an MCA error code indicating a ROB time-out. At this
point, the system requires a hard reset.
Workaround: It is possible for BIOS code to contain a workaround for this erratum.
Status: For the steppings affected see the Summary of Changes at the beginning of this
section
E65. Snoop probe during FLUSH# could cause L2 to be left in shared state
Problem: During a L2 FLUSH operation using the FLUSH# pin, it is possible that a read request
from a bus agent or other processor to a valid line will leave the line in the Shared
state (S) instead of the Invalid state (I) as expected after flush operation. Before the
FLUSH operation is completed, another snoop request to invalidate the line from
another agent or processor could be ignored, again leaving the line in the Shared
state.
Implication: Current desktop and mid range server systems have no mechanism to assert the
flush pin and hence are not affected by this erratum. A high-end server system that
does not suppress snoop traffic before the assertion of the FLUSH# pin may cause a
line to be left in an incorrect cache state.
Workaround: Affected systems (those capable of asserting the FLUSH# pin) should prevent
snoop activity on the front side bus until invalidation is completed after asserting
FLUSH#, or use a WBINVD instruction instead of asserting the FLUSH# pin in order
to flush the cache.
Status: For the steppings affected see the Summary of Changes at the beginning of this
section.
E66. Livelock May Occur Due to IFU Line Eviction
Problem: Following the conditions outlined for erratum E44, if the instruction that is currently
being executed from the evicted line must be restarted by the IFU, and the IFU
receives another partial hit on a previously executed (but not as yet completed) store
that is resident in the store buffer, then a livelock may occur.
Specification Update 71