Intel SL3QA - Pentium III 550 MHz Processor Specification page 53

Errata
Problem: This errata only affects multiprocessor systems where a lock variable address is
marked cacheable in one processor and uncacheable in any others. The processors
which have it marked uncacheable may stall indefinitely when accessing the lock
variable. The stall is only encountered if:
• One processor has the lock variable cached, and is attempting to execute a cache
lock.
• If the processor which has that address cached has it cached in its L2 only.
• Other processors, meanwhile, issue back to back accesses to that same address
on the bus.
Implication: MP systems where all processors either use cache locks or consistent locks to
uncacheable space will not encounter this problem. If, however, a lock variable's
cacheability varies in different processors, and several processors are all attempting
to perform the lock simultaneously, an indefinite stall may be experienced by the
processors which have it marked uncacheable in locking the variable (if the conditions
above are satisfied). Intel has only encountered this problem in focus testing with
artificially generated external events. Intel has not currently identified any
commercial software which exhibits this problem.
Workaround: Follow a homogenous model for the memory type range registers (MTRRs),
ensuring that all processors have the same cacheability attributes for each region of
memory; do not use locks whose memory type is cacheable on one processor, and
uncacheable
nonhomogenous memory model.
Status: For the steppings affected see the Summary of Changes at the beginning of this
section.
E26. MOV With Debug Register Causes Debug Exception
Problem: When in V86 mode, if a MOV instruction is executed on debug registers, a general-
protection exception (#GP) should be generated, as documented in the Intel
Architecture Software Developer's Manual, Volume 3: System Programming Guide,
Section 14.2. However, in the case when the general detect enable flag (GD) bit is
set, the observed behavior is that a debug exception (#DB) is generated instead.
Implication: With debug-register protection enabled (i.e., the GD bit set), when attempting to
execute a MOV on debug registers in V86 mode, a debug exception will be generated
instead of the expected general-protection fault.
Workaround: In general, operating systems do not set the GD bit when they are in V86 mode.
The GD bit is generally set and used by debuggers. The debug exception handler
should check that the exception did not occur in V86 mode before continuing. If the
exception did occur in V86 mode, the exception may be directed to the general-
protection exception handler.
Status: For the steppings affected see the Summary of Changes at the beginning of this
section.
E27. Upper Four PAT Entries Not Usable With Mode B or Mode C Paging
Specification Update
on others. Avoid page table aliasing, which may produce a
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