Intel SL3QA - Pentium III 550 MHz Processor Specification page 87

Errata
Workaround: Erratum can be avoided by placing a guard page (non-present or non-executable
page) as the last page of the segment or after the page that includes the code
segment limit.
Status: For the steppings affected see the Summary of Changes at the beginning of this
section
E108. EFLAGS, CR0, CR4 and the EXF4 Signal May be Incorrect after
Shutdown
Problem: When the processor is going into shutdown due to an RSM inconsistency failure,
EFLAGS, CR0 and CR4 may be incorrect. In addition the EXF4 signal may still be
asserted. This may be observed if the processor is taken out of shutdown by NMI#.
Implication: A processor that has been taken out of shutdown may have an incorrect EFLAGS,
CR0 and CR4. In addition the EXF4 signal may still be asserted.
Workaround: None identified
Status: For the steppings affected see the Summary of Changes at the beginning of this
section.
E109. Performance Monitoring Event FP_MMX_TRANS_TO_MMX May Not
Count Some Transitions
Problem: Performance Monitor Event FP_MMX_TRANS_TO_MMX (Event CCH, Umask 01H)
counts transitions from x87 Floating Point (FP) to MMX™ instructions. Due to this
erratum, if only a small number of MMX instructions (including EMMS) are executed
immediately after the last FP instruction, an FP to MMX transition may not be
counted.
Implication: The count value for Performance Monitoring Event FP_MMX_TRANS_TO_MMX may be
lower than expected. The degree of undercounting is dependent on the occurrences
of the erratum condition while the counter is active. Intel has not observed this
erratum with any commercially available software.
Workaround: None identified.
Status: For the steppings affected see the Summary of Changes at the beginning of this
section.
Specification Update
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