Intel SL3QA - Pentium III 550 MHz Processor Specification page 14

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Summary Tables of Changes
Plans
MC2_STATUS MSR has model-specific error
NoFix code and machine check architecture error
code reversed
Mixed cacheability of lock variables is
NoFix
problematic in MP systems
MOV with debug register causes debug
NoFix
exception
Upper four PAT entries not usable with Mode
NoFix
B or Mode C paging
Data breakpoint exception in a displacement
NoFix
relative near call may corrupt EIP
RDMSR and WRMSR to invalid MSR may not
NoFix
cause GP fault
SYSENTER/SYSEXIT instructions can
NoFix implicitly load null segment selector to SS
and CS registers
PRELOAD followed by EXTEST does not load
NoFix
boundary scan data
Far jump to new TSS with D-bit cleared may
Fixed
cause system hang
INT 1 instruction handler execution could
NoFix
generate a debug exception
COMISS/UCOMISS may not update EFLAGS
Fixed
under certain conditions
Fixed Transmission error on cache read
Potential loss of data coherency during MP
NoFix
data ownership transfer
Misaligned Locked access to APIC space
NoFix
results in hang
Floating-point exception signal may be
Fixed
deferred
Memory ordering based synchronization may
NoFix
cause a livelock condition in mp systems
System bus address parity generator may
Fixed
report false AERR#
NoFix System bus ECC not functional with 2:1 ratio
Processor may assert DRDY# on a write with
NoFix
no data
GP# fault on WRMSR to
NoFix
ROB_CR_BKUPTMPDR6
Machine check exception may occur due to
Fixed
improper line eviction in the IFU
ERRATA
Specification Update