Intel SL3QA - Pentium III 550 MHz Processor Specification page 86

transferring to ring 0.
available software.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes
E105. Unaligned Accesses to Paging Structures May Cause the Processor to
Hang
Problem: when an unaligned access is performed on paging structure entries, accessing a
portion of two different entries simultaneously, the processor may live lock.
Implication: When this erratum occurs, the processor may live lock causing a system hang.
Workaround: Do not perform unaligned accesses on paging structure entries.
Status: For the steppings affected see the Summary of Changes at the beginning of this
section.
E106. INVLPG Operation for Large (2M/4M) Pages May be Incomplete
under Certain Conditions
Problem: The INVLPG instruction may not completely invalidate Translation Look-aside Buffer
(TLB) entries for large pages (2M/4M) when both of the following conditions exist:
• Address range of the page being invalidated spans several Memory Type Range
Registers (MTRRs) with different memory types specified
• INVLPG operation is preceded by a Page Assist Event (Page Fault (#PF) or an
access that results in either A or D bits being set in a Page Table Entry (PTE))
Implication: Stale translations may remain valid in TLB after a PTE update resulting in
unpredictable system behavior.
commercially available software.
Workaround: Software should ensure that the memory type specified in the MTRRs is the same
for the entire address range of the large page.
Status: For the steppings affected see the Summary of Changes at the beginning of this
section.
E107. Page Access Bit May be Set Prior to Signaling a Code Segment Limit
Fault
Problem: If code segment limit is set close to the end of a code page, then due to this erratum
the memory page Access bit (A bit) may be set for the subsequent page prior to
general protection fault on code segment limit.
Implication: When this erratum occurs, a non-accessed page which is present in memory and
follows a page that contains the code segment limit may be tagged as accessed
86
Intel has not observed this erratum on any commercially
Intel has not observed this erratum with any
Errata
Specification Update