Intel SL3QA - Pentium III 550 MHz Processor Specification page 44

Workaround: If a system implementation must support both SMM and MCEs, the first thing the
SMM handler code (when an I/O restart is to be performed) should do is check for a
pending MCE. If there is an MCE pending, the SMM handler should immediately exit
via an RSM instruction and allow the machine check exception handler to execute. If
there is not, the SMM handler may proceed with its normal operation.
Status: For the steppings affected see the Summary of Changes at the beginning of this
section.
E9. Branch Traps Do Not Function If BTMs Are Also Enabled
Problem: If branch traps or branch trace messages (BTMs) are enabled alone, both function as
expected. However, if both are enabled, only the BTMs will function, and the branch
traps will be ignored.
Implication: The branch traps and branch trace message debugging features cannot be used
together.
Workaround: If branch trap functionality is desired, BTMs must be disabled.
Status: For the steppings affected see the Summary of Changes at the beginning of this
section.
E10. Checker BIST Failure in FRC Mode Not Signaled
Problem: If a system is running in functional redundancy checking (FRC) mode, and the
checker of the master-checker pair encounters a hard failure while running the built-
in self test (BIST), the checker will tri-state all outputs without signaling an IERR#.
Implication: Assuming the master passes BIST successfully, it will continue execution unchecked,
operating without functional redundancy. However, the necessary pull-up on the
FRCERR pin will cause an FRCERR to be signaled. The operation of the master
depends on the implementation of FRCERR.
Workaround: For successful detection of BIST failure in the checker of an FRC pair, use the
FRCERR signal, instead of IERR#.
Status: For the steppings affected see the Summary of Changes at the beginning of this
section.
E11. BINIT# Assertion Causes FRCERR Assertion in FRC Mode
Problem: If a pair of Pentium III processors are running in functional redundancy checking
(FRC) mode, and a catastrophic error condition causes BINIT# to be asserted, the
checker in the master-checker pair will enter shutdown. The next bus transaction
from the master will then result in the assertion of FRCERR.
Implication: Bus initialization via an assertion of BINIT# occurs as the result of a catastrophic
error condition which precludes the continuing reliable execution of the system.
Under normal circumstances, the master-checker pair would remain synchronized in
the execution of the BINIT# handler. However, due to this erratum, an FRCERR will
be signaled. System behavior then depends on the system specific error recovery
mechanisms.
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Errata
Specification Update