Intel SL3QA - Pentium III 550 MHz Processor Specification page 40

Case 2: In the second breakpoint reporting failure case, if a MOVSS or POPSS
Case 3: If they occur after a MOVSS or POPSS instruction, the INTn, INTO, and INT3
Case 4: If a data breakpoint and an SMI (System Management Interrupt) occur
Case 5: When an instruction that accesses a debug register is executed, and a
Case 6: Unlike previous versions of Intel Architecture processors, P6 family
Implication: When debugging or when developing debuggers for a P6 family processor-based
system, this behavior should be noted. Normal usage of the MOVSS or POPSS
instructions (i.e., following them with a MOV ESP) will not exhibit the behavior of
cases 1-3. Debugging in conjunction with SMM will be limited by case 4.
Workaround: Following MOVSS and POPSS instructions with a MOV ESP instruction when using
breakpoints will avoid the first three cases of this erratum. No workaround has been
identified for cases 4, 5, or 6.
Status: For the steppings affected see the Summary of Changes at the beginning of this
section.
E3. FLUSH# Servicing Delayed While Waiting for STARTUP_IPI in 2 way
MP Systems
Problem: In a 2-way MP system, if an application processor is waiting for a startup inter-
processor interrupt (STARTUP_IPI), then it will not service a FLUSH# pin assertion
until it has received the STARTUP_IPI.
Implication: After the 2-way MP initialization protocol, only one processor becomes the bootstrap
processor (BSP). The other processor becomes a slave application processor (AP).
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(DR6.bd). If additional breakpoint faults are matched during the call of the
debug fault handler, the processor sets the breakpoint match bits (DR6.bi)
to reflect the breakpoints matched by both the MOVSS or POPSS breakpoint
and the debug fault handler call. The processor only sets DR6.bd in either
situation, and does not set any of the DR6.bi bits.
instruction with a data breakpoint is followed by a store to memory which:
a) crosses a 4-Kbyte page boundary,
OR
b) causes the page table Access or Dirty (A/D) bits to be modified,
the breakpoint information for the MOVSS or POPSS will be lost. Previous
processors retain this information under these boundary conditions.
instructions zero the DR6.bi bits (bits B0 through B3), clearing pending
breakpoint information, unlike previous processors.
simultaneously, the SMI will be serviced via a call to the SMM handler, and
the pending breakpoint will be lost.
breakpoint is encountered on the instruction, the breakpoint is reported
twice.
processors will not set the Bi bits for a matching disabled breakpoint unless
at least one other breakpoint is enabled.
Errata
Specification Update