Intel SL3QA - Pentium III 550 MHz Processor Specification page 58

Status: For the steppings affected see the Summary of Changes at the beginning of this
section.
E38. Floating-Point Exception Signal May Be Deferred
Problem: A one clock window exists where a pending x87 FP exception that should be signaled
on the execution of a CVTPS2PI, CVTPI2PS, or CVTTPS2PI instruction may be
deferred to the next waiting floating-point instruction or instruction that would
change MMX™ register state.
Implication: If this erratum occurs the floating-point exception will not be handled as expected.
Workaround: Applications that follow Intel programming guidelines (empty all x87 registers
before executing MMX technology instructions) will not be affected by this erratum
Status: For the steppings affected see the Summary of Changes at the beginning of this
section
E39. Memory Ordering Based Synchronization May Cause a Livelock
Condition in MP Systems
Problem: In an MP environment, the following sequence of code (or similar code) in two
processors (P0 and P1) may cause them to each enter an infinite loop (livelock
condition):
P0
MOV [xyz], EAX
.
.
.
MOV [abc], val1
wait0: MOV EBX, [abc]
The EAX and EBX can be any general-purpose register. Addresses [abc] and [xyz]
can be any location in memory and must be in the same bank of the L1 cache.
Variables "val1" and "val2" can be any integer.
The algorithm above involves processors P0 and P1, each of which use loops to keep
them synchronized with each other. P1 is looping until instruction (6) in P0 is globally
observed. Likewise, P0 will loop until instruction (5) in P1 is globally observed.
58
P1
(1) wait1: MOV EBX, [abc]
CMP EBX, val1 (3)
JNE wait1 (4)
(6)
(7)
CMP EBX, val2 (8)
JNE wait0 (9)
NOTE
MOV [abc], val2 (5)
(2)
Specification Update
Errata