Intel SL3QA - Pentium III 550 MHz Processor Specification page 65

Errata
4. The IFU requests are periodically restarted.
The continued IFU restart attempts create additional DCU snoops, which prevent the
in-process locked operation from completing, keeping the DCU locked.
Implication: The system may hang
Workaround: It is possible for BIOS code to contain a workaround for this erratum.
Status: For the steppings affected see the Summary of Changes at the beginning of this
section.
E55. L2_DBUS_BUSY Performance Monitoring Counter Will Not Count
Writes
Problem: The L2_DBUS_BUSY (22H) performance monitoring counter is intended to count the
number of cycles during which the L2 data bus is in use. For some steppings of the
processor, the L2_DBUS_BUSY counter will not be incremented during write cycles
and therefore will only reflect the number of L2 data bus cycles resulting from cache
reads
Implication: The L2_DBUS_BUSY event counts only L2 read cycles.
Workaround: None identified
Status: For the steppings affected see the Summary of Changes at the beginning of this
section.
E56. Incorrect Sign May Occur On X87 Result Due To Indefinite QNaN
Result From Streaming SIMD Extensions Multiply
Problem: It is possible that a negative sign bit may be incorrectly applied to the result of an
X87 floating-point operation if it is closely preceded by a Streaming SIMD Extensions
(SSE) multiply operation. In order for this erratum to occur, the Streaming SIMD
Extensions multiply operation must result in an Indefinite Quiet Not-a-Number
(QNaN). Operations such as multiplying zero by infinity will result in an Indefinite
QNaN result.
Implication: If this erratum occurs, the result of an X87 floating-point instruction, which should be
positive, will instead be negative.
Workaround: It is possible for BIOS code to contain a workaround for this erratum.
Status: For the steppings affected see the Summary of Changes at the beginning of this
section.
E57. Deadlock
Combination
Problem: Intel's 32-bit Instruction Set Architecture (ISA) utilizes most of the available op-code
space; however some byte combinations remain undefined and are considered illegal
instructions. Intel processors detect the attempted execution of illegal instructions
and signal an exception.
application software.
Specification Update
May Occur Due
This exception is handled by operating system and/or
To Illegal-Instruction/Page-Miss
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