Intel SL3QA - Pentium III 550 MHz Processor Specification page 63

Errata
Problem: The act of one processor, or system bus master, writing data into a currently
executing code segment of a second processor with the intent of having the second
processor execute that data as code is called cross-modifying code (XMC). XMC that
does not force the second processor to execute a synchronizing instruction, prior to
execution of the new code, is called unsynchronized XMC.
Software using unsynchronized XMC to modify the instruction byte stream of a
processor can see unexpected instruction execution from the processor that is
executing the modified code.
Implication: In this case, the phrase "unexpected execution behavior" encompasses the
generation of most of the exceptions listed in the Intel Architecture Software
Developer's Manual Volume 3: System Programming Guide, including a General
Protection Fault (GPF). In the event of a GPF the application executing the
unsynchronized XMC operation would be terminated by the operating system.
Workaround: In order to avoid this erratum, programmers should use the XMC synchronization
algorithm as detailed in the Intel Architecture Software Developer's Manual Volume
3: System Programming Guide, Section 7.1.3.
Status: For the steppings affected see the Summary of Changes at the beginning of this
section.
E50. Processor Will Erroneously Report a BIST Failure
Problem: If the processor performs BIST at power-up, the EAX register is normally cleared
(0H) when the processor passes. The processor will erroneously report a non-zero
value (signaling a BIST failure) even if BIST passes.
Implication: The processor will incorrectly signal an error after BIST is performed.
Workaround: The system BIOS should ignore the BIST results in the EAX register.
Status: For the steppings affected see the Summary of Changes at the beginning of this
section.
E51. Noise Sensitivity Issue on Processor SMI# Pin
Problem: Post silicon characterization has demonstrated a greater than expected sensitivity to
noise on the processor's SMI# input, which may result in spurious SMI# interrupts.
Implication: BIOS/SMM code that is capable of handling spurious SMI events will report a spurious
SMI#, but should not be negatively impacted by this erratum. Systems whose BIOS
code cannot handle spurious SMI events may fail, resulting in a system hang or other
anomalous behavior.
Spurious SMI# interrupts should be controlled on the system board regardless of
BIOS implementation.
Workaround: Possible workarounds that may reduce or eliminate the occurrence of the
spurious SMI# interrupts include:
1. Use a lower effective pull-up resistance on the SMI# pin. This resistor must meet
the specifications of the component driving the SMI# signal.
Specification Update 63