Intel SL3QA - Pentium III 550 MHz Processor Specification page 56

Problem: A task switch may be performed by executing a far jump through a task gate or to a
new Task State Segment (TSS) directly. Normally, when such a jump to a new TSS
occurs, the D-bit (which indicates that the page referenced by a Page Table Entry
(PTE) has been modified) for the PTE which maps the location of the previous TSS will
already be set, and the processor will operate as expected. However, if the D-bit is
clear at the time of the jump to the new TSS, the processor will hang.
Implication: If an OS is used which can clear the D-bit for system pages, and which jumps to a
new TSS on a task switch, then a condition may occur which results in a system
hang. Intel has not identified any commercial software which may encounter this
condition; this erratum was discovered in a focused testing environment.
Workaround: Ensure that OS code does not clear the D-bit for system pages (including any
pages that contain a task gate or TSS). Use task gates rather than jumping to a new
TSS when performing a task switch.
Status: For the steppings affected see the Summary of Changes at the beginning of this
section.
E33. INT 1 Instruction Handler Execution Could Generate a Debug
Exception
Problem: If the processor's general detect enable flag is set and an explicit call is made to the
interrupt procedure via the INT 1 instruction, the general detect enable flag should be
cleared prior to entering the handler. As a result of this erratum, the flag is not
cleared prior to entering the handler. If an access is made to the debug registers
while inside of the handler, the state of the general detect enable flag will cause a
second debug exception to be taken. The second debug exception clears the general
detect enable flag and returns control to the handler which is now able to access the
debug registers.
Implication: This erratum will generate an unexpected debug exception upon accessing the debug
registers while inside of the INT 1 handler.
Workaround: Ignore the second debug exception that is taken as a result of this erratum.
Status: For the steppings affected see the Summary of Changes at the beginning of this
section.
E34. COMISS/UCOMISS May Not Update Eflags Under Certain Conditions
Problem: COMISS/UCOMISS instructions compare the least significant pairs of packed single-
precision floating-point numbers and set the ZF, PF, and CF bits in the EFLAGS
register accordingly (the OF, SF, and AF bits are cleared). Under certain conditions
when a memory location is loaded into cache, the EFLAGS may not get set.
Implication: The result of the incorrect status of the EFLAGS may range from no effect to an
unexpected application/OS behavior.
Workaround: It is possible for BIOS code to contain a workaround for this erratum.
Status: For the steppings affected see the Summary of Changes at the beginning of this
section.
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Errata
Specification Update